I am making 2-bit multiplier using half adders in verilog in Xilinx ISE 14.7, but I am getting the error. The modules codes are shown below:
module Half_Adder (S, C, A, B);
output S;
output C;
input A;
input B;
xor x1(S,A,B);
and a1(C,A,B);
endmodule
Verilog module of 2-bit multiplier:
module multiplier_2bit (A,B,C);
input [1:0] A;
input [1:0] B;
output [3:0] C;
wire w1;
wire [1:0] w2;
wire [2:0] S;
and g0(C[0], A[0],B[0]);
and g1(w1,A[0],B[1]);
and g2(w2[0],A[1],B[0]);
assign C[1] = S[0];
Half_Adder (S,C,w1,w2);
and g3(w1,A[0],B[1]);
and g4(w2[0],A[1],B[0]);
and g5(w2[1],A[1],B[1]);
assign C[2] = S[1];
Half_Adder (S,C,w1,w2);
endmodule
Please tell me where I am making mistakes.