Mismatch of requirements from JEDEC with recommendations Intel(Altera)

Question

I am studying the workings of DDR memory, in particular the recommendations for PCB layout. One of the intel documents (Table 1–24; Page 70) has the following wording: "Propagation delay of clock signal must not be shorter than propagation delay of DSQ signal at every device"

However, if this is compared with the requirements from JEDEC(Registration required for reading,Table 69, page 175): Where tCK is Average Clock Period = 8ns.

In the JEDEC standard I can clearly see the minus sign, which says that the DQS line is shorter. Is Intel(Altera) not DDR compliant or am I missing something?

Answer 1

Factors that contribute to the delay from one signal to another include but aren't limited to:

• Difference in propagation delays of the PCB traces.

• Difference in propagation delays from the chip's transceivers to pads.

• Difference in when the outputs change.

The Intel app note says the chip adjusts the third, and the requirement "Propagation delay of clock signal must not be shorter than propagation delay of DSQ signal at every device" is for the adjustment to work.

Oh by the way, about the second factor. With DDR3 being the standard of an interface, what's specified is the times when the signals reach the RAM chip's pads, so you don't have to worry about different propagation delays from the RAM chip's pads to its transceivers. However, some FPGAs have different propagation delays from transceivers to pads, and you need to account for that.