First, I want to apologize for my terminology here -- I'm a software engineer rather than EE and I'm a bit rusty.
I have a parallel SRAM chip that is being shared by 2 CPUs that requires 19 address lines and 16 data lines. This setup is a producer-consumer model, where 1 CPU only writes, and the other CPU only reads, and they trigger interrupts on each other through an external pin to signal that the data is ready to be read/is done being read. I'm sending about 40KB of memory every 20ms, and the consumer device requires a 100ns response time for reads.
Both CPUs are therefore using the same bus. I am able to set the producer CPU's pins to high impedance through software during reads, but the "consumer" CPU doesn't support that (and in-fact I have little control over it -- it isn't even aware that there is a producer, it just thinks it is reading a standard ROM chip). So, I need the "producer" CPU to be able to set all of those lines from the "consumer" CPU to high impedance during writes (basically implementing the OE functionality on memory chips) otherwise, my understanding is that my writes will be lost since the other CPU will act as a short circuit even if all address and data lines are set to low during the write.
What type of component do I use to add tri-state support to existing bus lines while breadboarding this out? Are there options that don't require wiring up a component for each line (say, a large switchboard that I can turn all lines "off" with a single input)?