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First, I want to apologize for my terminology here -- I'm a software engineer rather than EE and I'm a bit rusty.

I have a parallel SRAM chip that is being shared by 2 CPUs that requires 19 address lines and 16 data lines. This setup is a producer-consumer model, where 1 CPU only writes, and the other CPU only reads, and they trigger interrupts on each other through an external pin to signal that the data is ready to be read/is done being read. I'm sending about 40KB of memory every 20ms, and the consumer device requires a 100ns response time for reads.

Both CPUs are therefore using the same bus. I am able to set the producer CPU's pins to high impedance through software during reads, but the "consumer" CPU doesn't support that (and in-fact I have little control over it -- it isn't even aware that there is a producer, it just thinks it is reading a standard ROM chip). So, I need the "producer" CPU to be able to set all of those lines from the "consumer" CPU to high impedance during writes (basically implementing the OE functionality on memory chips) otherwise, my understanding is that my writes will be lost since the other CPU will act as a short circuit even if all address and data lines are set to low during the write.

What type of component do I use to add tri-state support to existing bus lines while breadboarding this out? Are there options that don't require wiring up a component for each line (say, a large switchboard that I can turn all lines "off" with a single input)?

Thanks

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  • \$\begingroup\$ what's the speed this runs at? \$\endgroup\$ Dec 19, 2021 at 19:09
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    \$\begingroup\$ You want a form of dual port ram. Look at something like 74HC157 for the address mux and 74HC245 for the data bus. Other parts of interest might be 74HC244,573,574. \$\endgroup\$
    – Kartman
    Dec 19, 2021 at 20:01
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    \$\begingroup\$ Logically it is a ‘dual port ram’. You can get dual port ram devices, but they tend to be expensive and probably not in the memory size you require. So that means you build one out of a number of chips. \$\endgroup\$
    – Kartman
    Dec 19, 2021 at 20:20
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    \$\begingroup\$ One can use also VHDL and FPGA devices ... intel.com/content/www/us/en/support/programmable/… or this vhdlguru.blogspot.com/2017/11/… or this asic-world.com/examples/vhdl/ram_dp_sr_sw.html \$\endgroup\$
    – Antonio51
    Dec 19, 2021 at 20:25
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    \$\begingroup\$ @Kartman do you want to provide your comment as the answer? \$\endgroup\$
    – cratonica
    Dec 19, 2021 at 20:29

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The classical way to do this is with Tri-state bus buffer ICs such as the 74xx244 or 74xx541 (where xx is LS, HC, HCT, LVC etc.), which have 8 buffers enabled by 1 or 2 control inputs. To do 19 address lines you would need 3 of them. Buffer ICs with more bits are also available (such as the 74ACT16244 which has 16 bits) but for various reasons it might be better to stick with 'standard' 8 bit ICs. If you only need a few more then adding an IC with fewer buffers (eg. 74xx125 which has 4 buffers) may be sufficient to get the total number you need.

If there are other devices on the 'consumer' data bus then you will probably also need Tri-state buffers on the data lines. For this you could use two 8 bit buffer ICs or a single 16 bit buffer IC.

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