# How to achieve signal gating with trigger input

I am currently working on a project that generates enable pulses of extremely diverse lengths from microseconds to days and under normal operation will start execution under a trigger input.

However, I am trying to add gated triggering so that the pulses will start running when the board turns on but will only output when the trigger is pulled high.

The gated triggering should only output pulses that occur completely during the period of triggering as shown below:

As you can see if the pulse generator goes high before triggering, then that pulse should not be collected for output. Standard gating logics along the lines of if (trigger AND pulse) do not work and because the pulses can be very long basic lookbehind methods such if (trigger = '1' AND pulse = '1' AND prev = '0') (with prev being the value of the pulse on the last clock cycle) do not work either.

I would attach code but since none of it achieves the correct outcome I'm not sure it would do much other than confusing.

• How come the 2nd clock pulse from the left doesn't get through? Commented Jun 24, 2022 at 19:36
• Sorry I meant to mention that I believe that's specific to the implementation by the company whose website the image is from. For my situation any pulses on or after the rising edge of the trigger are valid outputs, I will edit the post Commented Jun 24, 2022 at 19:39
• You need to be 100% clear to get a decent answer. If the picture is wrong draw your own. Commented Jun 24, 2022 at 19:49
• Talk about pulse edges either rising or falling please; that's less ambiguous. Easy to be ambiguous here. Commented Jun 24, 2022 at 19:51
• Possibly solved by a D flip-flop with D connected to trigger, clock connected to pulse_in, and asynchronous clear also connected to pulse_in. (VHDL code for such a flip-flop is very straightforward) Commented Jun 24, 2022 at 21:08

You can achieve the pulse-gating in your requirement, using a negative level-sensitive latch and an AND gate. Modified version of typical Clock Gating cells found in ASIC libraries.

If you describe the above circuit in HDL, you should see the expected behavior.

HDL (System Verilog):

module gated_pulse (

input  logic trig  ,
input  logic pb_in ,
output logic gated

) ;

logic trig_latched ;

always_latch begin
if (!pb_in) begin
trig_latched = trig ;
end
end

assign gated = trig & trig_latched & pb_in ;

endmodule


Simulation:

However, there is a catch if you are targetting an FPGA instead of ASIC. Most modern FPGAs don't support latches, and you don't want to infer an inferior one on LUTs. If this is the case, you can 'improvise' the above latch-based circuit using flip-flops on FPGAs.

HDL (System Verilog):

module gated_pulse (

input  logic trig  ,
input  logic pb_in ,
output logic gated

) ;

logic trig_registered ;

always_ff @(posedge pb_in, negedge trig) begin
if (!trig) begin
trig_registered <= 1'b0 ;
end
else begin
trig_registered <= trig ;
end
end

assign gated = trig_registered & pb_in ;

endmodule

• In VHDL I believe this would amount to tracking two clock edges in the same process which it cannot synthesize. However, I think it is possible that the FPGA I am utilizing does support latches, do you know if there's a way to verify this? Commented Jun 28, 2022 at 13:28
• @JohnB No, it's a single edge-triggered process. I guess you are not familiar with Verilog semantics. Equivalent to this would be a clocked process in VHDL with an active-low asynchronous reset (trig). process(clock, trig). It synthesised fine on Vivado, it should synthesise on any tool. Commented Jun 28, 2022 at 19:43
• If Latches are available in the vendor libraries for the FPGA you target, you may try out the first approach (but I doubt if it's available at all). Otherwise second one is the simpler one as it would synthesise on any target. Commented Jun 28, 2022 at 19:46
• oh interesting yeah I have never used verilog and assumed pos/neg edge corresponded to rising/falling_edge in vhdl, was slightly confused how you could have tracked two edges in one HDL but not the other, guess it makes sense now Commented Jun 28, 2022 at 19:50