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I have some relatively fast (1ns edge rate) signals going between microstrip (GND ref) to stripine (GND / VCC) through a via transition...

Track length isn't too long and vias are reasonably close to driver, so I'm not overly concerned about functionality... But it got me thinking.

Would a GND/VCC referenced stripline transitioning to a GND referenced microstrip appear as a significant discontinuity of the VCC plane after going through the via transition? Or would it be relatively benign? I suppose edge rate plays a big role in the "true answer", but lets assume a signal in the ballpark of 1ns rise time.

My initial instinct was that as the signal propagates down the stripline, the higher frequency content would return on both the GND / VCC planes... but then after transitioning through the via the VCC return would be open and there would be a pretty nasty discontinuity... even if the stripline and microstrip both have approximately the same Z0.

After thinking about it further I imagine it also depends upon the capacitive coupling between the VCC and GND planes... Perhaps a capacitor near the via transition would be the way to go if there was a true concern...

I suppose I could run a simulation to investigate... But... laziness prevails -- so, any thoughts?

Also... I found this article discussing how a stripline crossing a split on just one of it's reference planes behaves similarily to a microstrip crossing a split in it's single reference plane: https://www.signalintegrityjournal.com/articles/1742-what-happens-when-stripline-signals-cross-split-power-planes ... This seems like an even "worse" scenario.

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  • \$\begingroup\$ Can you make a drawing of the stackup? Is it 4 or 6 layer? (More?) \$\endgroup\$
    – RemyHx
    Commented Jul 21, 2022 at 5:29

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Would a GND/VCC referenced stripline transitioning to a GND referenced microstrip appear as a significant discontinuity of the VCC plane after going through the via transition? Or would it be relatively benign?

For digital signals at bit rates that allow a 1 ns edge speed (let's say, no higher than 500 Mbps), it's probably fairly benign.

But of course you will reduce your risk of having problems if you reduce the reflections at this discontinuity.

Perhaps a capacitor near the via transition would be the way to go if there was a true concern.

Agreed. To minimize the ground return discontinuity, it's best to place a capacitor between VCC and GND as close as you can to the microstrip-stripline transition.

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