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Since my last board flopped, I looked at it again and noticed a ground loop (because the DB9 casing completed the loop).

Now I adjusted my board so that there is no loop of any kind. Instead, I'm running a VCC track next to a GND plane with 1mm clearance right underneath the 40-pin DIP AT89S52 microcontroller (on opposite side of course since I'm doing single-sided PCB). I'm also planning to add a couple of 0.047uF decoupling capacitors.

For clarity, I added a picture of part of my circuit. I highlighted the ground wire in red and will convert it to a plane after so I don't waste etchant.

The circled green items are the 0.047uF ceramic decoupling capacitors.

They say ground loops are bad, but is vcc next to ground this close bad as well? and would modifying my clearance between the two planes affect microcontroller operation? and no I won't use 0 clearance or I'll blow the batteries up.

plane

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    \$\begingroup\$ If you have made progress on your previous question you should follow up there and resolve that before posting a new one. It sounds however as you are misusing the term ground loop, rather what you may have had there was a very long high impedance ground path. \$\endgroup\$ Commented Oct 7, 2018 at 17:18
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    \$\begingroup\$ "Ground loops are bad" is something I think usually applies to long cables, like meters in length, in which case they pick up inductive noise. It is rarely a problem on PCBs. \$\endgroup\$
    – jpa
    Commented Oct 7, 2018 at 18:23
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    \$\begingroup\$ I'm concerned you say you're only planning to add decoupling,, suggesting it wasn't there before. Every digital IC must have decoupling, and that's really non-optional. Micros often have specific requirements for how to do it - see the datasheet. It's usually good practise for analogue ICs too, although generally less critical there. \$\endgroup\$
    – Graham
    Commented Oct 7, 2018 at 22:54

3 Answers 3

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They say ground loops are bad, but is vcc next to ground this close bad as well?

Nope. Consider: the coupling between the two is largely capacitive, and by reducing clearance you increase the capacitance. However, you already are adding capacitors between them, so if anything it's to the good. This principle does not hold for two signal conductors, as the coupling can cause cross-talk, especially if one line is digital with a lot of sharp transitions and the other is low-level analog, but it's fine for VCC/ground. There are other situations where coupling can get you in trouble, but there is no indication they apply here.

The thing to look out for is leakage between the two. In the pcb world, the usual rule of thumb is 1 mil (1/1000 inch) of separation per volt of difference. So, as long as VCC is less than about 40 volts, 1 mm separation is just fine.

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In general, it's good to run Vcc as close as possible to the ground copper that will carry its return current. This reduces the size of the current return loop, which minimizes radiated emissions and improves radiated susceptibility.

If the potential on VCC might be over 50 V, then you need to start thinking about creepage and clearance distances. But I doubt this is the case here, since you're talking about powering a microcontroller.

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To achieve even lower inductance, widen either or both of VDD and GND traces (neither traces are a large region of copper metal, or foil as used in fabricating the PCB, so neither is a "plane"). By using that 1mm minimum separation all along that region, you will better exploit those two capacitors in supplying transient currents to the microcontroller.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ Indeed the OP does not seem to understand what a "ground plane" is: an entire PCB layer of copper dedicated only to Gnd. The purpose is to minimize the inductance of signal traces. A HF current loop minimizes its magnetic energy by letting the return current through the ground plane automagically follow a parallel path under the signal trace. That is why a ground plane must be uninterrupted except by small vias, so as to not break the path of the return current. This does wonders for EMC, at very little PCB layout effort. \$\endgroup\$
    – StessenJ
    Commented Oct 8, 2018 at 12:22
  • \$\begingroup\$ The return current is not completely under the signal trace. Particularly at lower frequencies, such as 100KHz, lots of the current will be out to the sides and NOT under the signal trace. \$\endgroup\$ Commented Oct 14, 2018 at 3:22
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    \$\begingroup\$ I'm a video engineer, we group 100 kHz with DC. My first job was a video amplifier for 100V pkpk, -3dB at 30 MHz. It's then that you realize that the circuit diagram is very incomplete, and also that a few pF of extra trace capacitance are a significant load at ~10V/ns. That's where (capacitive) current goes in one end of a wire but doesn't come out the other end. \$\endgroup\$
    – StessenJ
    Commented Oct 15, 2018 at 6:06
  • \$\begingroup\$ @ StessenJ Yes. At 5pF stray (or unavoidable), at 10 volts/nanosecond so those pixels are will defined, using I = C * dV/dT, you have 5pF * 10 billion volts/second = 50 milliAmps into the parasitic paths. What was the Grid capacitance you were driving? \$\endgroup\$ Commented Oct 17, 2018 at 4:18
  • \$\begingroup\$ Cathode, not Grid, and on paper it was some 10 pF. Add to that the behavior of the transistors, not eager to switch off in a class-B configuration. You will understand that it got very hot around my amplifier, and that I had to avoid high frequency test pictures or I my amp would blow up. I also learned that it is difficult to do measurements in such a circuit, E and M fields radiate directly into your probes. I had to plug the bare end of the probe into a coaxial socket, with minimal loops. Current loops are always a problem so you quickly learn to build compact circuits. \$\endgroup\$
    – StessenJ
    Commented Oct 18, 2018 at 6:25

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