I am designing a 16 bit CPU in Logisim Evolution.
I have already designed single clock cycle instructions.
I have 19 bits to control.
I tried using the register and clock divider circuit to send data in a pipeline. It works, but it outputs a floating value between two parts of a sequence. Also it takes 6 clock cycles to split 38 bits of data and send it in sequence. Basically I'm saying it doesn't work.
I need a way to mask 38-bit data and send it in a sequence of two 19-bit frames in 2 clock cycles.