I am designing a 16 bit CPU in Logisim Evolution.

I have already designed single clock cycle instructions.

I have 19 bits to control.

I tried using the register and clock divider circuit to send data in a pipeline. It works, but it outputs a floating value between two parts of a sequence. Also it takes 6 clock cycles to split 38 bits of data and send it in sequence. Basically I'm saying it doesn't work.

I need a way to mask 38-bit data and send it in a sequence of two 19-bit frames in 2 clock cycles.

Current variant of instruction pipeliner


1 Answer 1


Split it into 2x19 bits using a wiring splitter, then use a multiplexer to select the current part.

You already know how to make a signal that changes on every clock cycle. So use that signal in a multiplexer to select the low part on even clock cycles and the high part on odd clock cycles (or vice versa).


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