As a part of my Cadence based project, I chose the topic 'Optimising power, area and timing for a 32x8 SRAM unit'. Though this is possible using NC-Verilog or by manually constructing the schematic and simulating, we have been instructed to use the Encounter Tool alone. Is it possible to create the SRAM array digitally using Verilog? Is it possible to specify for analogue parts such as transistors their widths etc. by writing a Verilog code?
Some tools will infer RAM. They have already thought about area, for example. See your vendor's document for details.
NC-Verilog is for functional simulation. It doesn't track area and timing. For that you need to worry about synthesis to a specific vendor's library.
Analog parts aren't supported by Verilog.
No, verilog does not specify things at such a low level. Verilog describes behavior, it is up to a synthesis tool to infer a specific implementation.
You can synthesize the netlist manually by picking cells that you want from your cell library and instancing them in verilog, but there's no verilog instruction to choose how a certain behavioral statement will be synthesized. Any instructions for such would be specific to your synthesis tool, and not to verilog.