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Consider the case where L1 cache miss occurred and is being serviced by L2 cache which could take many cycles (may go to main memory in case of L2 cache miss). In the meantime L1 cache is idle, in that case can we use L1 cache to service a different memory request that could hit in L1?

In other words, can we use L1 cache to service other memory requests until L2 cache responds with data for a previous L1 cache miss.

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    \$\begingroup\$ On what specific microarchitecture? I'm sure some high-end superscalar CPU with a fancy load-store unit can have multiple loads in flight and service one of them while another handles a cache miss. I'm also sure that some CPU is fully incapable of doing this. \$\endgroup\$
    – nanofarad
    Commented Apr 17, 2023 at 15:04
  • \$\begingroup\$ @nanofarad thanks for reply, I know that in order processor cannot do this. I am looking at this in terms of out of order processor that has load store queues. \$\endgroup\$
    – HWDesigner
    Commented Apr 17, 2023 at 15:05
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    \$\begingroup\$ If it is an out of order superscalar processor, then probably it can. To know for sure, check the microarchitecture manual for your device and see what it says about servicing multiple concurrent loads. \$\endgroup\$
    – user1850479
    Commented Apr 17, 2023 at 15:07
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    \$\begingroup\$ if an out-of-order processor would stop processing every time there would be a cache miss, there would be no point making it out-of-order. \$\endgroup\$
    – Criticizing Israel not allowed
    Commented Apr 17, 2023 at 15:19
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    \$\begingroup\$ @SaiGautham, actually, in-order processors could theoretically do that. There was a claim that they could win back some of the performance of a full-blown out-of-order design by simply allowing load operations (and their dependency chains) to bypass stalled operations. You can read about "load slice" machines here - dl.acm.org/doi/abs/10.1145/2749469.2750407 \$\endgroup\$
    – Leeor
    Commented Apr 24, 2023 at 16:59

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