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I'm designing a very simple CPU to be built on a custom PCB. I designed the CPU in LogicCircuit, and it seems to work. But I'm wondering it a specific part of the CPU will also work in real life.

I implemented the JMP instruction as follows (cycle counter increases on falling edge):

  • Cycle 1: PC Output Enable onto address bus is active, PC Output Enable into the ALU is active, PC Write Enable is active (to latch the increased PC from the ALU). On rising edge, latch the instruction from ROM and latch the increased PC from the ALU into the PC register at the same time.
  • Cycle 2: PC Output Enable onto address bus is active, PC Write Enable is active. On rising edge, latch the new PC value from ROM)

My question is now, is it problematic that in Cycle 1 im latching the new PC value and the instruction at the same time. My thinking is that the instruction from ROM will be latched first before the increased PC value is latched. In the simulation this seems to work, but im not sure if im getting into any race condition in real life.

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  • \$\begingroup\$ Can I suggest you draw a timing diagram, it would really help \$\endgroup\$
    – jonathanjo
    Oct 23, 2023 at 9:35
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    \$\begingroup\$ I'd like to see a detailed diagram along with descriptions. Normally, the PC is not incremented by the common ALU but instead has it's own special incrementor. Competing with the regular ALU is not desired. In your case, it may be something you want because of the extra logic needed. But I'd like to see the details. \$\endgroup\$ Oct 23, 2023 at 9:52

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So you're saying that the new PC value is the second word of the instruction in the ROM. As long as the PC is a truly edge-triggered register, there will be no problem. It will capture the output of the ROM, and its output, along with the output of the ROM, cannot possibly change soon enough to violate the hold time requirement at the input of the PC register.

This is generally true of synchronous logic -- you can connect the output of one register directly to the input of another register on the same clock, and no data setup/hold time errors will occur.

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  • \$\begingroup\$ Cool, thanks! :) \$\endgroup\$
    – RenX
    Oct 23, 2023 at 12:31

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