I am designing a state machine in Verilog HDL to identify a specific number sequence. I must make it in structural.
When I design the DFF with a behavioral style, everything is great, but with the structural DFF, my waveform simulation goes wrong.
Here is my structural DFF and waveform:
Here is my behavior DFF and waveform:
I must make it in structural.
That is incorrect. You must question the reasoning behind that claim.
Using a structural model for sequential logic like a flip-flop is the wrong way to achieve what you want in Verilog. You should always use a behavioral model for a flip-flop. The Verilog language and simulators are designed to use behavioral modelling for this.
Another reason is that you should always write Verilog code at the highest level of abstraction because it is much easier to understand the code. The behavioral model essentially has only 2 lines of code, whereas the structural has 5 lines, 5 gate instances and several internal nets. The behavioral model clearly shows the design intent. The structural is more difficult to understand, leading to your problem.
Perhaps you were given this exercise by a professor. Maybe the point of the exercise is for you to untangle that mess of gates and nets. If that is the case, then you need to start analyzing every net in the design at every moment in time. You should check every connection and compare it against whatever schematic model you have. If you don't find any obvious connection errors, then you need to look at waveforms of all the internal signals and compare them against your expectations. This is time-consuming and is a huge disadvantage as compared to the behavioral model.
Another approach is to simulate a single ffd instance in its own testbench to see if it works as expected. It is much easier to prove if a single component works properly than it is to prove a collection of components work.
Keep this in mind: the structural model with the nand instances may have combinational feedback loops without delays, which means you are always trying to set nodes in your circuit with different values at the same time. This results in unknowns (x).
But to answer your actual question, the problem is that your "structural" DFF isn't an edge-triggered FF at all -- it's just a latch.
