I am trying to add test points for in circuit tests (ICT.) To keep all test points on top layer, the easiest way is to add pads to the vias.
My questions are:
Can the vias be located off-center to the pads (as shown) (need to fix some clearance issue)?
Yes, I don't see any drawbacks to this scheme. If you aren't putting a lot of force (enough force to deform the copper) then it probably won't matter where you put the via. A lot of test pads for pogos don't have vias at all and only traces attached.
Is it true that the probe tip may damage the structure of the via, causing reliability issue?
If you mean DMM probe then yes, but there is a chance to damage the copper with or without the via. Usually test pads are only used a few times over their lifetime anyway and usually only during test when a product is developed and also during manufacturing. In most of these cases the pads will only be used a 'handful' of times (lets say ~3-10 with a max of 20). Pogo pins are usually round and provide force over a large region and not a deformable force (they have springs for this reason).
I don't put vias in test-point pads.
It's not the via being damaged you need to be concerned with, it's the pogo-pin tips being damaged you need to think about.
If your test-pads are big enough to put a via into them, they're probably way to big to begin with. 1.0mm diameter is way more than enough; depending on your pogos and other tolerance-stack factors including those of your bed-of-nail pogo test jig, even 0.5mm might be enough.
Remember, in any production test-jig, they're being pressed onto test-pads thousands of times. Each time, if the pogo-pin point gets pushed into a approximately-centred via, because of drill location tolerance it's going to introduce lateral flex on the pogo-pin-head stalk that otherwise wouldn't need to happen. They will fail quicker, which means more down-time on your test-jig, which means you need more of them to keep production lines unblocked.
