We've heard about regular clock skew but here the clock skew has a minimum and max values.
The propagation delay (\$t_{pd}\$) of a logic gate is the time taken to produce a valid output given a valid input. Now, \$t_{pd}\$ typically depends on gate inputs and environmental factors like temperature and voltage and therefore takes on a range of values. The maximum possible delay for a given spec is denoted as (\$t_{pd_{max}}\$ or \$t_{max}\$).
The contamination delay (\$t_{cd}\$) of a logic gate is the time taken to produce an invalid output given an invalid input and takes on a range of values. The minimum possible delay for a given spec is denoted as (\$t_{cd_{min}}\$ or \$t_{min}\$). Note that given an input to a logic gate it first transitions from its stable or valid state to an invalid state before settling to the final valid state. Thus, \$t_{min}\$ is always in terms of \$t_{cd}\$ and \$t_{max}\$ in terms of \$t_{pd}\$.
The same logic applies to clock skew. Clock skew between two registers, occurs due to delays introduced in the clock path due to routing, buffers etc. whose delay can take on a range of values. The 'corner' case delays being \$t_{skew_{max}}\$ and \$t_{skew_{min}}\$
also I'm not sure but can I simplify it even further and subtract the small buffer before the clock of FF1 from the second clock buffer?
Your simplification is correct and no, don't move the buffer delay. You need it to calculate clock skew.
I would like to see a timing diagram and the process of creating it, and generally the method for solving these problems, since I understand circuits better when I'm given their timing diagrams.
Here is a simple timing diagram with a positive skew \$t_{skew}\$. The D_FF input denotes the inputs of the flip-flop and Q_FF its output. Q_FF1 changes after \$t_{cq_{FF1}}\$ and D_FF2 changes after \$t_{pd}\$.
Setup time constraint
Initially, I'll assume zero clock skew. To prevent setup violations, we need to ensure that the data launched from FF1 at clock edge 1 should arrive at FF2 (D_FF2) before it's clock edge 2 is triggered.
Data path delay = \$t_{cq_{FF1}} + t_{pd} + t_{setup_{FF2}}\$
Clock path delay = \$T_{clk}\$ (Since data is captured at clock edge 2)
Setup time constraint
$$
T_{clk} \geq t_{cq_{FF1}} + t_{pd} + t_{setup_{FF2}}
$$
Now, when there is a positive clock skew in the circuit, you are essentially pushing clock edge 2 of FF2 further by \$t_{skew}\$ (check waveform), and thus relaxing the constraint. So now the constraint becomes
$$
T_{clk}+t_{skew} \geq t_{cq_{FF1}} + t_{pd} + t_{setup_{FF2}}
$$
Now to bring in the worst case scenarios for the inequality. The clock should assume the max possible data path delay. And the min possible clock path delay (or skew).
$$
min(T_{clk}+t_{skew}) \geq max(t_{cq_{FF1}} + t_{pd} + t_{setup_{FF2}})
$$
Hold time constraint
Hold violations at FF2 occur when the its input D_FF2 is not held constant for atleast \$t_{hold}\$ after clock edge 1. But at clock edge 1 we also have FF1 data being launched which will eventually propagate its way to D_FF2 and change its value. We should ensure that this propagation from FF1 to D_FF2 happens only after \$t_{hold}\$.
$$
t_{cq_{FF1}} + t_{pd} \geq t_{hold_{FF2}}
$$
When a positive skew is introduced, clock edge 1 of FF2 is being pushed by an additional \$t_{skew}\$ with respect FF1's clock edge. Data propagation from FF1 now needs to wait an additional \$t_{skew}\$ in addition to \$t_{hold}\$. The hold constraint becomes
$$
t_{cq_{FF1}} + t_{pd} \geq t_{hold_{FF2}} + t_{skew}
$$
Considering the worst case scenario
$$
min(t_{cq_{FF1}} + t_{pd}) \geq max(t_{hold_{FF2}} + t_{skew})
$$
We need to determine if the t_hold and t_setup conditions are met with a positive skew of 1ns, so is it fair to say that when we look at the path from FF2 to FF1 the skew is actually -1 ns?
When data flow is from FF1 (launch FF) to FF2 (capture FF), skew is always defined as the difference between clock arrival at FF2 with respect to FF1 (\$t_{clk_{FF2}}-t_{clk_{FF1}}\$). Negative skew arises when the clock edge triggers at the capture FF before the launch FF.
