D-Flip-Flop Hold and Setup Timing Requirements

Question

Update: The answer is 28ns for sure

Giving the following circuit and timing table:

Question: It's known that the time between positive-edge and negative-edge of the clock (which comes after) is required to be 13ns or bigger. and that the input X gets updated when the clock reaches negative-edge. what's the minimal value of clock cycle time so that the circuit works with no problems?

Note: Clock cycle isn't symmetric (For example it could be 80% up and 20% down).

Final Answer: 28ns

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I tried to solve this one using a similar technique to what Mitu Raj suggested here: D-Flip-Flop Hold and Setup Timing

In order to make sure that the circuit works with no problems I need to make sure that Both Hold and Setup requirements are met, So I made the following check:

T_hold: T_cd(FF1)+T_cd(OR) >= T_hold(FF2) T_cd(FF1)+2 >= 2? Always True

T_setup: T_in+T_pd(OR)+T_setup(FF2) <= T_clc (T_in=time where clock is up) T_up+5+7 <= T_up+T_down 12 <= T_down

So we have one requirement 12 <= T_down which is already given (We know that 13 <= T_down)

Where did I make a mistake, and how to solve this one?

Answer 1

what's the minimal value of clock cycle time so that the circuit works with no problems?

Clearly, Setup is the relevant one for the analysis. Because Hold has no relation with clock period. However, you can crosscheck Hold in all paths with the given values to make sure that no path has hold violation.

For the time being, ignore the input-to-FF path from x to FF1.

Consider the rest of the three FF-to-FF timing paths -

• \$\text{Clk-to-Q1} \rightarrow \text{AND} \rightarrow \text{FF1} \$
• \$\text{Clk-to-}\overline {Q1} \rightarrow \text{OR} \rightarrow \text{FF2} \$
• \$\text{Clk-to-}\overline {Q2} \rightarrow \text{OR} \rightarrow \text{FF2} \$

From given values of propagation delays, the worst-delay path (critical path) is -

• \$\text{Clk-to-Q1} \rightarrow \text{AND} \rightarrow \text{FF1} \$

Setup analysis for that path - $$T_{clk\rightarrow Q_1}+T_{pd(AND)}+T_{setup}\le T_{clk}$$ $$\implies 28 \text{ ns} \le T_{clk}$$

This COULD be the minimum the clock period of the clock. But to conclude it, you have to see the requirement at the input path to FF1 from x. It has to satisfy the timing as well for \$T_{clk} = 28 \text { ns.}\$ Otherwise, it could be the critical path. This path is -

• \$\text{input at x} \rightarrow \text{AND} \rightarrow \text{FF1}\$

Setup analysis for this path - $$T_{in}+T_{pd(AND)}+T_{setup}\le T_{clk} \tag 1$$

It's known that the time between positive-edge and negative-edge of the clock (which comes after) is required to be 13 ns or bigger. And that the input X gets updated when the clock reaches negative-edge.

The meaning of this is, the input delay at x has to be assumed as 13 ns at least. So if we plug in value 13 ns in equation (1) -

$$\bbox[6px,border:1px solid green] {26\le 28 \text { ns}} \text { -- satisfies!}$$

Initial Conclusion

If the input delay at x becomes > 15 ns for instance, it becomes the critical path, and the minimum clock period will then have to be more than 28 ns. So the minimum clock period in which the circuit can operate under given conditions is 28 ns.

Exception

Honorable mention to @StainlessSteelRat's answer, +1. Consider our critical path - \$\text{Clk-to-Q1} \rightarrow \text{AND} \rightarrow \text{FF1} \$

Actually if the flip-flop FF1 has no preset input, there is no way Q of FF1 to become 1 in the given circuit. Or in other words, this path never toggles. This kind of path is called False Path in digital designs. False paths can always be safely ignored in timing analysis as it can be pessimistic for setup analysis (especially in this particular circuit).

Final Conclusion

Considering the false path into picture, the critical path now becomes any of the remaining two timing paths. Both have 27 ns delay. And this clock period still satisfies equation (1). So the minimum clock period in which the circuit can operate under given conditions is 27 ns.

You can point out this to your professor, maybe he missed out this.

Answer 2

28ns is NOT the answer. And the key point is in the OP Question What's the minimal value of clock cycle time so that the circuit works with no problems?

From Understanding Sequential Circuit Timing:

\$t_{cd}\$ is hold time on input to insure input does not change until output changes. It is the minimum gate propagation delay. It is not input setup time and as can be seen from the drawing, \$t_{cd}\$ is contained inside propagation delay \$t_{pd}\$. So hold times can be excluded!

There are two possible timing paths:

FF1:

$$t_{pd}(AND) + t_{setup}(D-FF) + t_{pC->Q}(D-FF) = 28ns$$

FF2:

$$t_{pd}(OR) + t_{setup}(D-FF) + t_{pC->Q}(D-FF) = 27ns$$

So if you go by FF1, you get 28ns, which would be the minimum time for the full circuit.

But the circuit is flawed in a number of ways.

If you look at FF1, to get a 1 on Q, you need a 1 on D. But if Q is 0, you cannot get a 1 on D, no matter what state x is in. So the only thing which changes is z (it toggles) and it is 27ns.

The logic flaw of FF1, makes this a false path, which makes the true answer 27ns. This is a fundamental logic problem, which would come directly under finding the minimum time.

Second flaw is no gate input setup times [\$t_{in}(AND)\$ or \$t_{in}(OR)\$] in given info. So true answer would be larger.