We have a Stratix V FPGA on which we want to run a 1G Ethernet PHY and MAC. Because we don't have a readily available 125MHz reference clock, we are considering using a PLL internal to the FPGA to generate a 125MHz clock from a clock of a different frequency.
PLLs internal to FPGAs are "known" to have have high jitter. Would the jitter requirements of 1G Ethernet be held if we used an internal PLL as a reference clock for our 1G PHY/MAC? What are the IEEE requirements on deterministic jitter for the reference clock of a 1G MAC?