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Designing a D-FF in Virtuoso to create 90 degrees phase shift

I am currently trying to design a digital circuit in Cadence to produce a 90 degrees phase shift to a CLK signal within my current circuit. Below is an image of a D-FF setup as well as the output ...
soccernismo's user avatar
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Wireopt variable in cadence virtuoso ADE simulator window

I am wondering about a variable in my simulator & output window in cadence virtuoso. It is wireopt. It is there by default when I start any simulation in ADE/ADE XL window. And the value is this. ...
aguntuk's user avatar
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2 answers
143 views

Designing an oscillator circuit in Cadence Virtuoso, but not sure why the comparator portion is not working

I am currently in the process of designing and testing an oscillator design which consists of a current reference and a comparator based on common gate topology (right hand side circled in red.) The ...
soccernismo's user avatar
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Export Cadence Virtuoso Schematic to tikz

To export the layout to tikz, there's this great tool available: https://github.com/electronics-and-drives/ml2tikz I thought there was a similar tool to export the schematic to tikz but I can't find ...
Holzbaum's user avatar
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DC analysis of a CMOS comparator

I'm designing a strongarm latch comparator in virtuoso using gpdk90 and I'm not seeing what I'm doing wrong while doing DC simulations. I want to extract the comparator's offset but the output is ...
Scully's user avatar
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1 answer
677 views

Sizing an CMOS StrongArm Latch comparator on Virtuoso from scratch

I'm currently designing an CMOS comparator and I'm a little bit lost regarding sizing the transistors. I was taught to use the Id formula, but for that to work I need to have muCox, and I do not. Can'...
Scully's user avatar
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1 answer
51 views

How to make one time changing state pulse?

I'm undergraduate learning the analog circuit design. I want to make a signal that changes its state only one time when the input pulse signal changes its state at first. I'm trying to use D-flip flop,...
xoo's user avatar
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2 votes
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301 views

Cadence Virtuoso CMOS layout: MIMcap become unrecognised after instantiating a new component

I have a really weird issue with the layout of my design (TSMC 0.18um BCD). I have three components (A, B and C), all of which are LVS and DRC clean and sitting in their own respectable NBLs. ...
Nitrogen's user avatar
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160 views

The following branches form a loop of rigid branches (shorts) when added to the circuit in Cadence Virtuoso

I'm trying to build a Full Adder in Cadence Virtuoso using 2inp NAND Gate symbol. But I'm getting the following error, This is the circuit, Schematic of the symbol, What is the mistake and the ...
Dominic Immanuel's user avatar
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2 answers
343 views

All the currents and voltages are shown zero in my circuit - Cadence Virtuoso

In the following circuit, I do not know why all the currents and voltages are shown zero? My simulation just contains the "DC" simulation. After performing DC simulation, all the node ...
mohammad rezza's user avatar
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1 answer
879 views

What is the meaning of a negative capacitance? - Cadence Virtuoso

What is the meaning of a negative capacitance in cadence virtuoso? Here in the following image, I just want to find the capacitance of transistors using "print-->DC operating point". Can ...
mohammad rezza's user avatar
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1 answer
259 views

What is the meaning of "a" and "z" in capacitor value - Cadence Virtuoso

What is the meaning of "a" and "z" in capacitor value? Here is the image: I think "a" is angstrom, But I am not sure about it.
mohammad rezza's user avatar
1 vote
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46 views

How can I find critical field in tsmc65 transistor parameter?

How can I find critical field in tsmc65 transistor parameters? Critical field is the field which electron velocity in transistor go into the saturation region.
mohammad rezza's user avatar
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1 answer
654 views

How can I find tsmc65N (or 65nm feature size) NMOS parameters definition in Cadence Virtuoso?

How can I find tsmc65N (or 65nm feature size) NMOS parameters definition in Cadence Virtuoso? They are all abbreviated and there is not any guide there. For example, I want to know the value of "...
mohammad rezza's user avatar
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1k views

How to find (mobility*Cox) and Vth

How to find "mobility*Cox" and "threshold voltage" of NMOS in cadence virtuoso? I have performed DC analysis in schematic environment and using NMOS model parameters, I tried to ...
mohammad rezza's user avatar
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1 answer
444 views

What is the meaning of "Unit Size NMOS (W=5*325nm/L=5*65nm)"

What is the meaning of the following sentence: Simulate a Unit Size NMOS (W=5 * 325nm/L=5 * 65nm) and PMOS (W=5325nm/L=565nm) with in CMOS technology. Well, this transistor is a MOSFET with 65nm ...
mohammad rezza's user avatar
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Erroneous oscillation voltage for LC Tank in Cadence Virtuoso

I simulated an LC tank with an ideal inductor and capacitor. The inductor's initial condition was 0 and the capacitor's was 300 mV. I expected it to oscillate with an amplitude of 300 mV, but it ...
SAYAN KUMAR's user avatar
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628 views

Cadence Virtuoso Schematic: Input pin goes to 2 different nets

I have a silly problem regarding input pins connecting to 2 different nets of a circuit in cadence virtuoso. Due to non-sharable agreement, I cannot share the actual circuit. But I can provide simple ...
aguntuk's user avatar
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1 vote
1 answer
163 views

Allowed amount of input wreal data type at verilog-ams

I'm a newbie at using Verilog-ams and also I want to write a module for flash ADC for a specific application. I need to confine my voltages reference so I wrote this Verilog-ams code for testing input ...
Marziye Hasanshahi's user avatar
1 vote
1 answer
167 views

I want to implement this active inductor design in my circuit

I'm trying to use an active inductor instead of the inductor in my class e power amplifier, however, I'm having difficulties in getting the required values for the parameters, Cds, Cgs, Cgd, and Ceq, ...
CruderSein's user avatar
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61 views

Figure of Merit for sizing P-MOS and N-MOS in Inverter circuit

I am trying to design a basic circuit block of inverter (Analog circuit) in Cadence Virtuoso schematic in 22nm technology. It will be used for non-overlapping clock generator. I need to size the P-MOS ...
aguntuk's user avatar
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0 votes
1 answer
309 views

Setting multi-fingers in MOSFET in series configuration in Cadence Virtuoso schematic

I am trying to figure out to set multi-fingers (nf = 3) for MOSFET (both P-MOS and N-MOS.) I know I can increase the length directly. As connecting MOSFETs in series increases length, can I somehow ...
aguntuk's user avatar
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311 views

How to add NCSU FreePDK45 to Cadence Virtuoso Library?

I'm looking for a comprehensive guide on how to add FreePDK45 to Cadence Virtuoso Library (2015 version). The installation guides included are not clear for first timers, and other resources available ...
eln05's user avatar
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1 answer
1k views

Transmission gate conducting in OFF state

Here is a part of my circuit that I am trying to simulate in cadence virtuoso. It has two transmission gates, the one in path of charging the capacitor is on and other one is OFF. Supply voltage is ...
Sparsh's user avatar
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4 votes
1 answer
793 views

6T SRAM cell write operation not working as expected in virtuoso

I am trying to play around a 6T SRAM cell by simulating it's write operation in Cadence Virtuoso. The NMOS and PMOS specifications are 120/45 nm and 310/45 nm. The Bit select is kept at constant 1 and ...
Sparsh's user avatar
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