21
votes
Accepted
What's the difference between setting SysTick Interrupt in NVIC and using it as an exception?
A couple of definitions first:
In the Cortex-M programming manual, an Exception is anything that breaks the normal program flow, and invokes a handler from the vector table, and Interrupts are a ...
11
votes
What is the meaning of the keyword "__weak" in this callback function in HAL GPIO function?
The __weak keyword means that the function can be overridden by creating another function with the same declaration.
Many of the interrupt-functions etc. in the STM ...
- 5,612
8
votes
Accepted
Why operations on float variable are performed on a double? STM32F401RE, MDK-ARM v5
I'm assuming that temperature[1] is an integer type of some sort.
The subexpression (temperature[1] >> 5)*0.125 contains ...
- 20.7k
8
votes
What is the meaning of the keyword "__weak" in this callback function in HAL GPIO function?
As explained in this stackexchange question a function defined as "_weak" can be overwritten by a user-defined function with the same name.
It basically is a default function. If you don't ...
- 9,749
5
votes
Accepted
Are peripherals in microcontrollers purely hardware or do they run code?
That GPIO pin logic is almost certainly done in hardware.
The reason they have different registers for set/clear/toggle a pin is to prevent read-modify-write problems. It also makes the software ...
- 12.5k
5
votes
What is the meaning of the keyword "__weak" in this callback function in HAL GPIO function?
It has nothing to do with STM32 or embedded programming.
It's just a compiler dependent extension to tell the C compiler that an object is weakly declared, as by default objects are strongly declared.
...
- 172k
4
votes
What's the difference between setting SysTick Interrupt in NVIC and using it as an exception?
The fundamental difference between the systick and peripheral interrupts is that the systick is specified by ARM to be at IRQ 6 (0x003C) when it is available in the core.
It is also part of the ARM ...
- 24k
4
votes
Accepted
Can Cortex M4 data watchpoint trigger an interrupt without a debugger?
I looked deeper into the documentation and I found out that DebugMon_Handler is enabled by:
...
- 9,096
4
votes
Accepted
Range of the write protection registers on STM32 (WRP1AR etc)
I don't see how the reference manual is unclear, so my answer is basically just a quote:
The user area in Flash memory can be protected against unwanted write
operations. Two write-protected (WRP) ...
- 18.1k
4
votes
How do you set an STM32F4 IRQ handler without using the HAL?
If you use the standard startup code, it defines the vector names. So you write a standard C function with the vector name and that will be the IRQ handler. The HAL just provides the handler for you ...
- 172k
4
votes
Bit banding in Arm cortex M4
The bit specific address is an alias for an operation conducted on a specific bit of an address in the bit band target region.
If you wish to make a simultaneous change to multiple bits, you should ...
- 33.6k
4
votes
Accepted
ARM Cortex-M4 VFMA (fused multiply-add) performance? 3, 2 or 1 clock? Forwarding?
In the TRM, there is the statement:
Floating-point arithmetic data processing instructions, such as add, subtract, multiply, divide, square-root, all forms of multiply with accumulate, as well as ...
- 7,999
3
votes
3
votes
Accepted
How does ARM CMSIS functions access Core registers in unprivileged mode?
This question seems to arise from a confusion between Thread vs Handler modes and Privileged ...
- 33.6k
3
votes
Uclinux vs Linux
As answered by its homepage, or its wikipedia page:
μClinux is a variation of the Linux kernel, previously maintained as a fork, that targets microcontrollers without a memory management unit (MMU)....
- 73.4k
3
votes
Accepted
GPIO Access on Cortex-M4 : Read-Modify-Write vs Atomic
You assume that all operations on IO ports are at bit level. I wrote an external LCD interface a while ago that used Px0..Px7 for the data interface, and Px8 for the write control. This allowed me to ...
- 5,117
3
votes
Accepted
How to set by software interrupt of USART in NVIC? - in fact emulate it
You can try using NVIC_SetPendingIRQ() or the software trigger register STIR as in
...
- 10.5k
3
votes
What causes this "stuck address" behavior in STM32 peripherals?
The three topmost pins of port A is used for JTAG. Therefore the pins must have those default values in the mode register to work as JTAG pins.
On the other hand, you are reading from a peripheral ...
- 172k
3
votes
Dealing with denorms in the ARM Cortex M4 FPU
From https://shop.elsevier.com/books/the-definitive-guide-to-arm-cortex-m3-and-cortex-m4-processors/yiu/978-0-12-408082-9, if the exponent value is zero and the fraction part of a double is not 0, it'...
- 30.6k
2
votes
Accepted
I2C Communication Signal Issue
I'm not familiar with the Kinetic MCU, but on a different MCU I have had the same waveform when I misconfigured the SDA line as a regular output instead of configuring it as an open-drain output.
You ...
- 3,626
2
votes
FreeRTOS causes SYSTICKACT (HardFault) exception
Both the HAL and FreeRTOS use the SysTick - CubeMX does this by calling the FreeRTOS systick handler (vPortSysTickHandler() I think, but might have the name wrong) from its own systick handler. In ...
- 401
2
votes
Why am I not able to compile this assembly code?
In VMOV, the F32 format expects the following argument as immediate value:
Any number that can be expressed as \$\pm n \times 2^{–r}\$, where n and r are
integers, 16 <= n <= 31, 0 <= r &...
- 2,674
2
votes
STM32F4 executable stack?
The stm32 can happily execute from RAM, so yes, this is possible. Depending on which variant of STM32F4 you have different sections of SRAM are attached to the I-bus, this is detailed in the reference ...
- 4,577
2
votes
Accepted
Atmel SWD. Enabling normal GPIO function on the SWO pin
I kinda forgot i posted this question here, but in the meantime I found the answer on some other site that I can't find right now.
You can disable the SWO functionality simply through this code:
<...
- 201
2
votes
Accepted
STM32 SYSCLK and CORTEX SYSTEM TIMER
One, SYSCLK is the clock the other clocks in the processor are derived from, including but not limited to core clock and peripheral clocks, the other is the clock ...
- 4,577
2
votes
Accepted
STM32F4xx bootloader & interrupts
I think I found a missing link myself.
Instead of jumping to the Reset_Handler itself, jumping to the Reset_Handler + 1 helps. This sets the LSB to 1 an gives an indication that it is thumb code. For ...
- 71
2
votes
Accepted
SAM Timer counter / atmel ASF
unfortunately this code doesn't work. (it has a bug that goes to infinite loop).
It is not an infinite loop: you do not clear the interrupt bit so when you return the interrupt is still pending and ...
- 14.6k
2
votes
What is the difference between system clock and peripheral clock in case of arm Cortex M4 architecture?
You're mixing up MCU core architecture (e.g. "Cortex-M4"), which is the same for all ARM Cortex-M4 ICs, no matter whether they were designed by NXP, ST, SiLabs,…, and peripheral design, which was done ...
- 100k
2
votes
Help understanding ARM Cortex-M4 SBC instruction
Forget everything you think you know, for a moment. Let's just consider the idea of how subtraction takes place in a processor.
It's very convenient to develop a logical unit that supports ADD and ...
- 78.7k
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