A couple of definitions first:
In the Cortex-M programming manual, an Exception is anything that breaks the normal program flow, and invokes a handler from the vector table, and Interrupts are a subset of Exceptions, coming from the peripherals outside the ARM core. Because SysTick is implemented in the Cortex-M core, it is considered an exception, but not ...
Since the M4 core (and pretty much any other CPU used in a microncontroller) is turing complete, the answer to your first question is yes, conditional on the other details of the MCU.
In particular, while the CPU itself is certainly capable of the instructions required to do JPEG compression, it must have enough RAM to implement whatever algorithm is chosen,...
You have two problems. The first is that the MCU runs at 168MHz if it has been set up that way, and your compiler may not do that by default. Setting up the clock is a bit arcane. ST provides an excel-based tool to help you create a setup file, and then the file needs to be put in the correct place and some other files need to be edited.
I recommend this ...
Complete is never possible. You can just raise the effort & cost.
It has nothing to do with 'cortex m4', but everything with the manufacturer's implementation of the chip.
Your chip has the usual set of read/execute protection bits. I doubt much is known in the (open) literature about the detailed weaknesses of such a new chip.
Very generally ...
The CPU should not give you any problems, as you say the instruction set of an M4 is a superset of the M0/M0+ instruction set. Note that the timing might be different, so busy-wait based timing might not work the same.
Peripherals can be a PITA, I would not assume they are the same unless the datasheets read the same.
In fact it's quite easy - there are multiple methods. I outlined one in this thread.
Basically you will have two separate pieces of software running. Consider the following setup (it's just an example):
Bootloader (Flash address 0x0000 - 0x1000)
Application (Flash address 0x1000 - 0x2000)
(of course, those are dependent on your requirements)
Now, the ...
The fundamental difference between the systick and peripheral interrupts is that the systick is specified by ARM to be at IRQ 6 (0x003C) when it is available in the core.
It is also part of the ARM Cortex, clocked by the same clock and thus synchronous.
The other exceptions (interrupts) are up to the manufacturer to decide what base priority (offset) and ...
I don't see how the reference manual is unclear, so my answer is basically just a quote:
The user area in Flash memory can be protected against unwanted write
operations. Two write-protected (WRP) areas can be defined, with page
(2 KByte) granularity. The area is defined by a start page offset and
an end page offset related to the physical Flash ...
I'm not familiar with these devices, but in the user manual it is mentioned that:
The Sleep state of the system corresponds to the Sleep state of the
CPU. The state is entered via WFI or WFE instruction of the CPU. In
this state the clock to the CPU is stopped. The source of the system
clock may be altered. Peripherals clocks are gated according to ...
I looked deeper into the documentation and I found out that DebugMon_Handler is enabled by:
CoreDebug->DEMCR = CoreDebug_DEMCR_TRCENA_Msk /*enable tracing*/ |
CoreDebug_DEMCR_MON_EN_Msk /*enable debug interrupt*/;
Now I get DebugMon_Handler interrupt when the watchpoint is hit.
As answered by its homepage, or its wikipedia page:
μClinux is a variation of the Linux kernel, previously maintained as a fork, that targets microcontrollers without a memory management unit (MMU).
There is no difference at this point. It's just a layer that handled memory management for a device that did not have it, particularly micro controllers.
This question seems to arise from a confusion between Thread vs Handler modes and Privileged vs Unprivileged modes.
To quote the Cortex M4 Technical Reference Manual:
The processor enters Thread mode on Reset, or as a result of an exception return. Privileged and
Unprivileged code can run in Thread mode.
The processor enters Handler mode as a ...
1.Do starting with Cortex-M4 is good idea? (because of ARMv7, Harvard mem arch etc)
Yes, why not? If you are programming in C language, I think you won't feel the difference (only the compiler will). In the other hand if you are programming in assembly, then there are differences of course.
2.between NXP, ST and TI Cortex-M4 based MCUs which is better ...
A lot of this depends on what you mean by "Family".
If you're asking for which manufacturer's product family is a good place to start, I'd recommend Atmel's SAM series basically because of the toolchain, at least if you're on windows.
ARM is unfortunately rather fragmented, in terms of manufacturer support and toolchains for windows.
Atmel has Atmel ...
The ARM Cortex M0 is the lowest and most simple architecture in the ARM family.
Personally I learned using the FRDM-KL25z development board from Freescale although there are a wide array of options.
There is an Arduino-like environment called mBed, which is very similar to Arduino although it is for ARM controllers. You can use mBed with many different ...
I use Eclipse IDE, with the gcc-arm compiler. They are both free.
Eclipse is an open source IDE, originally created for Java development. There's a surprisingly large community of developers who keep adding functionality, such as support for embedded processors!
You can debug via the ST-LINK/V2, and you can use the ST Standard Peripheral Library by ...
The TM4C123 has two CAN peripherals, but the Launchpad board seems to expose only one of them (CAN0) on its headers. At first glance that would suggest that you can't do it from one peripheral to another.
Two possible solutions spring to mind:
Most CAN modules support loopback mode, i.e. a module can be configured to receive its own transmission.
If you ...
Example 1 does not properly show any voltage source as Vref - it can come from ADVREF or VDD_MAIN
Example 2 has a potential divider (R307 and R306) forming a voltage that is buffered by the OP-AMP. This uses a voltage reference chip (a 4.096 shunt regulator) across the potential divider to keep things fairly stable if the power rail (VCC_P5V0) moves around.
I kinda forgot i posted this question here, but in the meantime I found the answer on some other site that I can't find right now.
You can disable the SWO functionality simply through this code:
CoreDebug_Type *core = CoreDebug_BASE;
core->DEMCR = (0<<CoreDebug_DEMCR_TRCENA_Pos);
Am I right with this calculation ~0x3 = ~(0000 0011) = 1111 1100 ?
Almost, stm32 is a 32 bit processor so it will be:
1111 1111 1111 1111 1111 1111 1111 1100
So when I do GPIOC->MODER &= ~0x3;, am I setting the first to bits of this register to 00 (input mode)?
For the description of each register you have to look hat this Reference Manual. For the ...
As brhans said, you can just use a standard JTAG. What I did on a recent design, I placed both a trace connector (for debugging) and a simple SWD connector (for production programming).
If you do want to put an Trace connector on your board, here are your answers:
Pin 7 is not fitted and acts as a key to prevent the connector from being plugged in ...
This is one method from here:
volatile unsigned long delay;
SYSCTL_RCGC2_R |= 0x00000010; // 1) activate clock for Port E
delay = SYSCTL_RCGC2_R; // allow time for clock to stabilize
You could also set up us the clock(s) and go do something else for a few cycles (initialize some stuff) but that's a potential bug in the future.
Edit: The ...
I'm not familiar with the Kinetic MCU, but on a different MCU I have had the same waveform when I misconfigured the SDA line as a regular output instead of configuring it as an open-drain output.
You can see that the slave is responding with an ACK and trying to drive SDA low but something (probably the Kinetic as I2C master) is driving SDA high thus you ...
Apperently your clock timer Timer0 is slower than data timer Timer1 so there nothing suprising in represented behaviour because your code skip every second event from Timer1 when you use while.
I think there enough one timer with max used frequency - is Timer1. More over there should be one timer because data and clock must be synchronous and this ...
Both the HAL and FreeRTOS use the SysTick - CubeMX does this by calling the FreeRTOS systick handler (vPortSysTickHandler() I think, but might have the name wrong) from its own systick handler. In FreeRTOS you can do the reverse by calling the HAL systick handler from FreeRTOS's tick hook function. Note however that, while FreeRTOS normally runs SysTick at ...
You assume that all operations on IO ports are at bit level. I wrote an external LCD interface a while ago that used Px0..Px7 for the data interface, and Px8 for the write control. This allowed me to directly stream a pixel (16-bit colour) to the display using a sequence of four GPIO_ODR writes. If I had used BSRR I would have had to translate the raw pixel ...
You do not. You buy the development board, in your case the MSP-EXP432P401R, and you use wires to the breadboard.
Or you buy a development board you can breadboard, mbed has some.
Putting this category of chips on a breadboard gives you a deluxe package of problems, if you are going that way, you'd better start funding this website.
You program that chip ...
I think I found a missing link myself.
Instead of jumping to the Reset_Handler itself, jumping to the Reset_Handler + 1 helps. This sets the LSB to 1 an gives an indication that it is thumb code. For the IRQ handlers it is documented in the ARM Information Centre.
Most (if not all) jumps in the generated code from C have an LSB 0 of zero (and interrupts ...