Unclocked, edge-triggered version of RS flip-flop?

Question

Is there such a thing as an edge-triggered RS flip-flop? That is, one input would, on rising edge, set the output to 1, and the other input would, on rising edge, set the output to 0. Falling edges would be ignored. I feel like this must exist, but I don't know what it would be called.

Answer 1

Yes, such a thing is possible, but it isn't more useful than more conventional flip-flops. Here's one way to make one:

^{simulate this circuit – Schematic created using CircuitLab}

The output is the XOR of two internal flip-flops. If they're different, the output is high; otherwise, the output is low.

REG1 will toggle on the rising edge of the S input only if the output is low; if the output is high, it won't change state.

Similarly, REG2 will toggle on the rising edge of the R input only if the output is high; if the output is low, it won't change state.

Note that there's a requirement that near-simultaneous rising edges on both S and R have a minimum spacing, basically determined by the delay time of the feedback gates.

Answer 2

In this realization, the flops should be designed so that the reset inputs will do nothing unless their logic levels suggest that the following dual-NOR latch is not in a metastable state (it's possible that depending upon the timing of input pulses to the latch, the clr input might perceive a runt pulse which would try to put one of the flops into a metastable state, but that could only happen if the other flop was cleanly high).

^{simulate this circuit – Schematic created using CircuitLab}

This design inherently relies upon non-negative propagation delays with the flops' asynchronous reset inputs, but that isn't generally a problem. A 74HC4066 PLL chip uses something a little bit like this, except that the flops feed a single gate rather than a latch, so that there are three states: If Input 1 was hit two or more times since the last Input 2 pulse, Flop 1 will be high. If Input 2 was hit two or more times since the last Input 1 pulse, Flop 2 will be high. If the last two pulses arrived on different inputs, neither flop will be high.

Answer 3

When you say edge triggered it sort of implies a clock edge. People are seeing this and forcing a clock signal somehow. But in your description you just describe two inputs which are triggered on the rising edge and ignore falling edges.

This is a similar situation to MS-CMOS, where the capture latches are implemented using SR. In MS-CMOS, it is always guaranteed that ONE of the S or R signals will rise and fall; and the other will not. So an SR latch suffices.

You also did not constrain whether after one signal rises, it will fall before the next. I will assume that this is not the case, and that if Signal1 rises and sets output to 1, and before Signal1 falls, Signal2 rises; that it should set the output to 0.

I believe you are looking for a SR NOR latch, modified to toggle in the S=R=1 state. This is often called a JK latch.

Lets call J = S1 = "one input would, on rising edge, set the output to 1"
Lets call K = S2 = "and the other input would, on rising edge, set the output to 0"

Both J and R = 0 to begin. Output state is indeterminate.

Then, J rises. This sets Q = 1.
Next, J falls. The output stays 1.
Next, K rises. The output is set to 0.
Next, K falls. The output stays 0.
Next, J rises. The output is set to 1.
Next, K rises. The output is set to 0. (this is JK toggle state, if this won't happen just use NOR SR latch)
Next, J falls. The output stays 0.
Next, K falls. The output stays 0.
...

Is this what you are looking for? Wiki link, showing truth table, gate level schematic

EDIT: Added fix for both inputs @ 1 simultaneously.

If you want both edges at once to toggle, generate a pulse to clock the flip flop. The pulse duration needs to be wide enough to toggle once but not twice. 1 or 3 inverters should work; I chose 3 in this case. The simple simulator didn't have 3 input ANDs so I just chained two 2-inputs back to back; either will work.

Edit2: Dave Tweed pointed out that holding one input high and repeatedly pulsing the other would toggle each time. Also he suggested combining SR with the pulse detectors. I have attached schematic and simulation below.

It is quite lean and low power/small (only 10 gates).

It will have indeterminate state if both inputs rise simultaneously (within the pulse width duration). Other implementations will have a similar effect to lesser or greater degree depending on the topology.

Answer 4

Simpler...I'll have to desribe rather than draw...

2 dtypes one exor gate.

xor:

op = overall o/p.

xor ips = both d type q's.

dtype1:

ck = set ip.

d = dtype 2 not q.

dtype2:

ck = reset ip.

d = dtype1 q.

clock d1 (set), q's become different, xor=1.

clock d2 (reset) q's become same, xor=0.

Answer 5

Yes, it is called an SR latch: See google's results

If you want to read more, hyperphysics has a good explanation here which transitions to clocked flip-flops here.

Remember -- a FF is not a latch :>

Answer 6

Have a look at the Wikipedia entry for the 555 timer. In bistable mode, it mentions a similar required action, although neg edge triggered and levels do interfere but one or both inputs can be capacitively coupled to keep the inputs as a pulse. Worked for me after some fiddling.