# What actually makes a flip-flop edge-triggered?

I understand the concept of level-triggered latches, as well as edge-triggered flip-flops. What I don't understand however, is what actually makes flip-flops positive/negative edge triggered. When comparing the circuit diagrams of an SR latch and a D flip-flop, I can't seem to find what exactly is present in the D flip-flop circuit that makes it trigger on the edge rather than on the level.

I have the following D flip-flop circuit:

When I tested this in logisim, it seemed that the circuit was actually level-triggered, since when I slowed down the clock to 0.25Hz, and would change the value of Data while the clock was on high (but past the positive edge), the values of Q and Q' would still update, despite what I've been told about the edge-triggered nature of flip-flops.

Am I missing something here? I have a feeling that this is a silly question, and I apologize if that is the case, but I really feel like I'm misunderstanding something fundamental about flip-flops.

• technically it is still level triggered .. but the data pin is latched so that changing the input does not propagate to the output immediately Dec 18, 2022 at 22:04
• FF is level-triggered when It is true if it can work with the level slowly rising or falling. This behavior is hidden "inside" the K-map for that FF. When it is edge triggered, the rising and falling are very important, and under one "trig value", it does not work (capacitive input for some clocked devices). Dec 19, 2022 at 12:42
• electronics.stackexchange.com/questions/205761/… Dec 19, 2022 at 12:51

I have the following D flip-flop circuit:

I would call it a D latch. I would call a circuit a flip-flop if it is edge triggered rather than level triggered. However, your circuit is not edge triggered. It is level triggered.

it seemed that the circuit was actually level-triggered, since when I ... change[d] the value of Data while the clock was on high (but past the positive edge), the values of Q and Q' would still update.

That is correct. It is level "triggered". The "clock" in your circuit is really an "enable".

What I don't understand however, is what actually makes flip-flops positive/negative edge triggered.

There are two (possibly more) ways to make a circuit edge triggered, rather than level triggered.

One way is to create (from the clock input) a very short pulse on a rising (or falling) edge of the clock. This can be done by making a delayed version of the clock (often an inverted as well as delayed) and recombining it with the original clock input. For example:

simulate this circuit – Schematic created using CircuitLab

Assuming the logical inverter has sufficient delay, when the input goes high, the output will go temporarily high. However, as soon as the output of the inverter goes low, the output will go low. Some variation of this circuit can be used to limit the "window" in which a change in the data input can result in a change in the output of a flip-flop.

A second approach to making an edge triggered flip-flop is to use feedback in such a way that when the clock pulse arrives at the flip-flop, the data is latched, and then the internal state of the flip-flop quickly moves to a stable state in which data inputs have no effect. Flip-flops designed along these lines include circuits like this:

You will notice that in this circuit, there are actually 3 latches. And there is feedback into the 2 latches on the left hand side of the schematic. This feedback is used to "move" these latches into states where they are impervious to future input changes. Only when the clock becomes inactive again, do these latches regain the ability to respond to input changes.

Although it uses feedback, and thus might be subsumed under the 2nd method mentioned above, the typical master-slave flip-flop is worth mention on its own. It does use feedback as shown in this schematic:

This circuit can be simulated here.

Unlike a transparent edge triggered flip-flop, the master-slave flip-flop delays the appearance of the input for a half-cycle of the clock. That is, there are two phases involved in moving the input to the output. Phase 1 latches the input, phase 2 moves the input to the output latch.

• If I remember well ..., the gate inverter after the CLK input has some "hidden levels" properties. Dec 19, 2022 at 12:47

This is a great question. It, of course, depends on the implementation of the D-flip flop.

When I was in grad school, I got the below implementation. Basically, in positive edge triggered, the value of D that was "stored" in the first latch stage makes the transmission gate input (~CLK) turn on and pass that value to the 2nd latch stage of the M/S Flip flop (to 'Q'). Simply changing the CLK signal pins would make it the opposite. Tell me if that doesn't make sense, I can add additional details.

Citation: Uyemura JP (John P. Introduction to VLSI Circuits and Systems / John P. Uyemura. J. Wiley; 2002.