I have this scheme from my lecturer of digital logic. It is supposed to be an edge-triggered D type flip-flop, with a reset so there's no undefined zone at the start of the simulation of this schematic. We're using Lattice Diamond to make these schematics and Active-HDL to simulate them.
Now everything's well except for one thing, which is what happens when my clock is rising and my D (which is input), is decreasing?
I've read on these forums that this is because of metastability and the inability to determine exactly what should be done. So I made this schematic and my simulation returns these results:
Where C is the Clock, D is input and Dinaminis is the output
You see the output rising on 30ns, when the Clock is increasing and D is decreasing. Then at 50ns, C is rising and D is rising too, but the flip-flop stops. Are these results okay or am I wrong somewhere? Does this flip flop use previous output to determine which output to choose? Thank you for all your answers