digital logic - positive edge-triggered d flip flop triggers when input is on the decreasing edge

Question

I have this scheme from my lecturer of digital logic. It is supposed to be an edge-triggered D type flip-flop, with a reset so there's no undefined zone at the start of the simulation of this schematic. We're using Lattice Diamond to make these schematics and Active-HDL to simulate them.

Now everything's well except for one thing, which is what happens when my clock is rising and my D (which is input), is decreasing?

I've read on these forums that this is because of metastability and the inability to determine exactly what should be done. So I made this schematic and my simulation returns these results:

Where C is the Clock, D is input and Dinaminis is the output

You see the output rising on 30ns, when the Clock is increasing and D is decreasing. Then at 50ns, C is rising and D is rising too, but the flip-flop stops. Are these results okay or am I wrong somewhere? Does this flip flop use previous output to determine which output to choose? Thank you for all your answers

Answer 1

No problem with the circuit. The problem is the way you have simulated. When you toggle D at the exact moment of the rising edge of the clock, the HDL simulator will take only its past value. For eg., in your design, you toggled D from 1-->0 @30 ns. But HDL simulator will take it as 1 for the rising edge @30 ns . This will create uncertainity of output even in real world too. In real world, the input D has to arrive and become stable before something called "setup-time" of the flip-flop. It has to remain stable even after the clock edge has appeared, for an amount of time called "hold-time". D should not change within this time window. Only then, the correct output is guaranteed. This is recommended to be followed while HDL simulation too.

Answer 2

You need to learn that an edge triggered flip-flop will not work if the D input is changing state at the same time as the active edge of the C clock input. Proper operation requires that the D input be at a stable state before the active clock edge. This is called the D input setup time. For real components (i.e. IC flip-flop chips) this setup time will be specified in the data sheet, usually as a minimum value needed to assure that meta-stability problems do not come into play.

For your discrete gate circuit you can learn from analyzing the circuit paths and knowing what the gate delays are to arrive at an understanding of what the setup time requirements are for that circuit.