can't solve latches

Question

I would like to ask if someone could help me with some latches in my desing. I am working with an aes encrypt core taken from opencores and I have described in vhdl the surrounding system to introduce an get the data to the core. When I simulate it, my design works properly but when I program my FPGA with the system's bitstream and I communicate whith it via hyperterminal It doesn't return me the correct encrypted data. I have tryed to many things to solve it but I don't manage to find the error, I was thinking that maybe some latches that there are in the system could be the problem. I post here just the lines were the latches are.

PD: the core communicates with zynq via axi and I am using a ZedBoard Zynq Evaluation and Development Kit (xc7z020clg484-1)

state control: latch in next_state

  begin  
    if (rising_edge(S_AXI_ACLK)) then
    if (S_AXI_ARESETN='0')then
      actual_state <= wait_state;
   else 
      actual_state <= next_state;
    end if;
  end if;
end process;

data input enable: latch in a<=Avalid_data_I; and b <= Avalid_key_I;

process (S_AXI_ARESETN, S_AXI_ACLK) 
        begin  
            if (rising_edge(S_AXI_ACLK)) then
                 if (S_AXI_ARESETN='0')then
                    a<=  '0';
                    a1<= '0';
                    b <= '0';
                    b1 <= '0';
                 else
                    a<=Avalid_data_I;
                    a1<= a;
                    b <= Avalid_key_I;
                    b1 <= b;
                    c <= valid_data;
                    c1 <=c;
                 end if;
            end if;
    end process;

finally I have a latch when I build the output: dat_encrip is a the output from the encryption core taken from opencores and out_encrypt is a internal register that will be read from the zynq.

      out_encrypt (31 downto 24) <= dat_encrip when (cnt=0 and    dato_valido= '1');
      out_encrypt (23 downto 16) <= dat_encrip when (cnt=1 and valid_data= '1');   
      out_encrypt (15 downto 8)  <= dat_encrip when (cnt=2 and valid_data= '1');
      out_encrypt (7 downto 0)   <= dat_encrip when (cnt=3 and valid_data= '1'); 

Thank you for your help and sorry If you find it difficult to understand me, because my English in not enough good.

Answer 1

I'm not sure whether the latches really are your problem, but those lines end up in latches:

out_encrypt (31 downto 24) <= dat_encrip when (cnt=0 and dato_valido= '1');
out_encrypt (23 downto 16) <= dat_encrip when (cnt=1 and valid_data= '1');   
out_encrypt (15 downto 8)  <= dat_encrip when (cnt=2 and valid_data= '1');
out_encrypt (7 downto 0)   <= dat_encrip when (cnt=3 and valid_data= '1');

Take a look at the first line, for example:

out_encrypt (31 downto 24) <= dat_encrip when (cnt=0 and dato_valido= '1');

This will assign a new value to out_encrypt(31 downto 24), but only when cnt=0 and dato_valido= '1'. If this expression evaluates to false, there's nothing new to assign to out_encrypt(31 downto 24) -- the synthesis tool will not have a choice but build a latch to store the old value. In other words, you will need an else clause here to assign an illegal value or do the assignments in a clocked process (ie. assign to a register).

More generally, any assignment that's not inside a clocked process and that does not specify a new value for every input combination will end up as a latch.

Answer 2

Something is not good with your process, it is written in a mixed way of process with async reset and sync reset. It is also missing reset for c and c1. I think that, for sync reset which Xilinx recommends, it should be:

process (S_AXI_ACLK) 
    begin  
        if (rising_edge(S_AXI_ACLK)) then
             if (S_AXI_ARESETN='0')then
                a<=  '0';
                a1<= '0';
                b <= '0';
                b1 <= '0';
                c <= '0';
                c1 <= '0';
             else
                a<=Avalid_data_I;
                a1<= a;
                b <= Avalid_key_I;
                b1 <= b;
                c <= valid_data;
                c1 <=c;
             end if;
        end if;
end process;