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I have a Serial-ATA Controller design working on almost any kind of Xilinx 7-series devices, except for the Artix-7 device, which gives me headaches...

The pure design (SATA 6.0Gb/s, 150 MHz design clock) can be implemented on my Artix-7 200T. If I add ILA cores (formerly known as ChipScope), the timing is not met.

What did I do the relax the situation: - added 2 pipeline stages in each ILA core - added 1 pipeline stage between GTP transceiver and the logic - used retiming, remap and wide placement as alternative implementation strategy

This images show the normal design flow. The ILA cores are far away from the SATAController (SATAC) and the 8-bit CPU (SoFPGA), but the controller still has failing paths (that's the only region with failing paths).

enter image description here

It feels like the Artix-7 is out of routing resources in some areas. How can I get a report indicating such a suspicion?

I also tried retiming, remap and wider placement strategies. The result is this:

enter image description here

The timing failure is almost the same...

P.S. The design uses only 178 of >300 BlockRAMs. I used Xilinx ISE to use almost every BlockRAM in other designs, but I never encountered such a behavior.

Edit:

Here is a heat map of all negative slack values per Slice (colored in red) enter image description here

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    \$\begingroup\$ In Altera Quartus there is something called LogicLock regions which allow you to constrain a partition or chunk of logic to a specific region. I presume there will be something similar for Xilinx (though not sure what it would be called). If you can do that, you should constrain the ILA to a region away from your logic (to stop it displacing important stuff), and add extra pipelining (unsconstrained to the region) to help with timing. \$\endgroup\$
    – Tom Carpenter
    Commented Aug 31, 2016 at 0:09
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    \$\begingroup\$ It may also be a case of false paths between the clock domain of the ILA and any other clock domains causing false paths which result in extra effort by the fitter (causing real paths to be treated with less priority and so failing timing) \$\endgroup\$
    – Tom Carpenter
    Commented Aug 31, 2016 at 0:10
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    \$\begingroup\$ I've had similar issues with SignalTap (again Altera equivalent of ILA), with failing paths being caused because sensitive paths were getting pushed apart by tap logic wanting to be closer to the signals being tapped. It was happening mostly where there was high BRAM density because the SignalTap BRAMs were forcing other BRAMs further apart. Once SignalTap was constrained to a region which was less critically filled, the problems went away. \$\endgroup\$
    – Tom Carpenter
    Commented Aug 31, 2016 at 0:18
  • \$\begingroup\$ @TomCarpenter The placement constraints are called PBlock :). As far as I can tell, there are no ILA cells in the SoFPGA or SATAC region, they are separated through 3 FF stages on each of the 151 trace signals. The probed design runs in the same clock domain as the ILA (150 MHz). All paths are constrained (no unconstrained, no failing inter-clock paths). The mentioned failing paths are all in the same clock domain, either in the SATAC or in the ILA itself. I found a routing congestion report, which says circa 54 % usage (hor. and vert.). Please see my neg. slack heat map added to my question. \$\endgroup\$
    – Paebbels
    Commented Aug 31, 2016 at 12:28
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    \$\begingroup\$ I found 2 issues: At first, the Artix-7 is 15 to 50 % slower than a Kintex-7. If I change the default speed grade from -2 to -3 all is fine (there is a safety margin of 200 ps compared to 670 ps neg. slack. So the speed grade -3 improves a 6.600 ns path by almost 0.970 ns! It seems as if the pure attachment of trace signals causes a higher fan out, which causes timing problems. Additionally, the trace routes go through the 100 MHz clock domain for the 8-bit CPU, which in turn causes (one out of 5 runs) issues in that clock domain. So long lines / route throughs cause issues on other lines. \$\endgroup\$
    – Paebbels
    Commented Aug 31, 2016 at 12:37

1 Answer 1

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You can get a detailed report by doing a design analysis in Xilinx Vivado. Run the following command in the tcl console : "report_design_analysis" It gives you the timing, complexity and congestion report of the implemented design. You can also run this report via going to Tools->Report->Report Design_analysis.

In this report, you can see which areas are causing congestion due to placing. Which Slices are fully used or what is the rent of such slices and/or routes.

I hope this was of help.

Regards, KWQ

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  • \$\begingroup\$ Thanks for this (to me unknown) report. How does it differ from my last image (the timing heat map)? \$\endgroup\$
    – Paebbels
    Commented Oct 26, 2016 at 17:09

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