Output voltage in MOS cascode amplifier

Question

I'll give a background to my main question:-

In a simple NMOS as shown, while constructing the small signal model of the MOSFET, when there is no resistance between V_dd and drain, NMOS is modeled only as a current source with i_d = g_m*v_in.

^{simulate this circuit – Schematic created using CircuitLab}

But now, when we put Rd, the drain voltage now also varies as

V_d + v_d = V_dd - (I_d+i_d)*R_d

(Upper case letters depict currents and voltages due to biasing and lower case letters depict small signal currents and voltages.)

Now, because of this variation in V_d, an r_o is introduced in the small signal model.

(Background ends here)________________________________________

Now, in a cascode amplifier such as this:-

Here, there is no R(resistor) anywhere.I'm unable to reason out why drain voltage of M₄ varies. Hence, what I think is that modelling M₄ with and r₀₄ in its small signal model wouldn't be correct. And hence, as I think that drain voltage of M₄ should be constant, so should be the drain voltage of M₃, and so, V_out should be constant. Please tell if V_out varies or not varies for this cascode amplifier.

Answer 1

Hence, what I think is that modelling M4 with and r04 in its small signal model wouldn't be correct.

And why would you think that? Isn't the \$r_o\$ of a MOSFET part of the MOSFET's small signal behavior?

Indeed there is no physical (drain) resistor present. But does there need to be?

Let's take some steps back and determine the small signal equivalent circuits for some configurations, for simplicity I'm using the non-cascoded versions:

^{simulate this circuit – Schematic created using CircuitLab}

The circuit around M2 also doesn't have a "real" drain resistor. There is only a DC current source I_DC2 but that DC currentsource is not an ideal current source. It has some output resistance, that's Rp_Idc2. Since it is a current source the output resistance is in parallel with the source.

To the right of M2's circuit is the equivalent small signal model. Note how Rd_Idc2 takes the same place as the "real" resistor Rd1 in the schematic around M1.

Now look at the 4 transistor schematic from your question, it says that M3 and M4 are a current source. Since these are transistors they will not behave as an ideal current source. So the same thing that I did for my circuit with M2 applies, if I know the output impedance of that (cascoded) current source together with gm of M1 (from your circuit) then I can calculate the small signal gain.

So, split the problem in two, use small signal analysis to determine the output impedance of M1 + M2 (from your circuit, where M2 is the cascode). How to calculate this will be explained in your textbook. The same applies for M3 + M4, with the only difference that no signal is applied at the gates.