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I'll give a background to my main question:-

In a simple NMOS as shown, while constructing the small signal model of the MOSFET, when there is no resistance between Vdd and drain, NMOS is modeled only as a current source with id = gm*vin.

schematic

simulate this circuit – Schematic created using CircuitLab

But now, when we put Rd, the drain voltage now also varies as

Vd + vd = Vdd - (Id+id)*Rd

(Upper case letters depict currents and voltages due to biasing and lower case letters depict small signal currents and voltages.)

Now, because of this variation in Vd, an ro is introduced in the small signal model.

(Background ends here)________________________________________

Now, in a cascode amplifier such as this:-

enter image description here

Here, there is no R(resistor) anywhere.I'm unable to reason out why drain voltage of M4 varies. Hence, what I think is that modelling M4 with and r04 in its small signal model wouldn't be correct. And hence, as I think that drain voltage of M4 should be constant, so should be the drain voltage of M3, and so, Vout should be constant. Please tell if Vout varies or not varies for this cascode amplifier.

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Hence, what I think is that modelling M4 with and r04 in its small signal model wouldn't be correct.

And why would you think that? Isn't the \$r_o\$ of a MOSFET part of the MOSFET's small signal behavior?

Indeed there is no physical (drain) resistor present. But does there need to be?

Let's take some steps back and determine the small signal equivalent circuits for some configurations, for simplicity I'm using the non-cascoded versions:

schematic

simulate this circuit – Schematic created using CircuitLab

The circuit around M2 also doesn't have a "real" drain resistor. There is only a DC current source I_DC2 but that DC currentsource is not an ideal current source. It has some output resistance, that's Rp_Idc2. Since it is a current source the output resistance is in parallel with the source.

To the right of M2's circuit is the equivalent small signal model. Note how Rd_Idc2 takes the same place as the "real" resistor Rd1 in the schematic around M1.

Now look at the 4 transistor schematic from your question, it says that M3 and M4 are a current source. Since these are transistors they will not behave as an ideal current source. So the same thing that I did for my circuit with M2 applies, if I know the output impedance of that (cascoded) current source together with gm of M1 (from your circuit) then I can calculate the small signal gain.

So, split the problem in two, use small signal analysis to determine the output impedance of M1 + M2 (from your circuit, where M2 is the cascode). How to calculate this will be explained in your textbook. The same applies for M3 + M4, with the only difference that no signal is applied at the gates.

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  • \$\begingroup\$ I agree with you for most of the part. But, where you say that because MOS are not ideal current sources and must have finite output resistance = ro4(for M4), that is what I think shouldn't be the case . I agree that MOS have finite output resistance but to model it, a varying Vds is needed which is absent in M4(source connected to Vdd and drain has nothing to vary its voltage). \$\endgroup\$ – Rohan Sep 11 '18 at 18:39
  • \$\begingroup\$ Finally, the absence of ro in M4 leaves no resistance to convert varying Id to varying voltage and leaves source voltage of M3 contant too. Can you please explain why should M4's small signal model contain ro4 when its Vds isn't varying at all because while deriving the small signal model, ro is modeled as d(Vds)/d(Id)(partial derivative).And thanks again for answering in so much detail. \$\endgroup\$ – Rohan Sep 11 '18 at 18:39
  • \$\begingroup\$ Your assumption that M4 has a constant Vds isn't correct. Indeed the change of Vds of M4 is significantly reduced by the cascode M3 but it is not reduced to zero. Read here: aries.ucsd.edu/NAJMABADI/CLASS/ECE102/12-F/NOTES/… for all the gory details about the MOS cascode. The same small signal model (without an input signal, so just ground Vi) applies to a cascoded PMOS used as a DC current source. \$\endgroup\$ – Bimpelrekkie Sep 11 '18 at 19:20
  • \$\begingroup\$ If your assumption that the Vds of M4 was true then indeed the DC current would be 100% independent of the output voltage. Meaning, a cascoded MOS would have an infinite output impedance. Do you think that that is a realistic and achievable property? In electronics there is nothing that's ideal, there's always a practical limit to the properties of any device. If you disagree I'd like to know and show me an example of such a device and what ideal (or infinite) property it has because then I will need to buy one asap. \$\endgroup\$ – Bimpelrekkie Sep 11 '18 at 19:26

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