VHDL: What is correct way to model open collector output for FPGA?

Question

I2C uses open collector outputs. FPGAs do not have such outputs. They do have tri state buffers though.

1. How should open collector output be defined in a VHDL for an FPGA?
2. How should open collector output be pulled high in testbench? i.e how model the pull up resistor e.g on SDA line that connects master to slave, in a testbench?

Answer 1

FPGAs have tri-state outputs :

sda <= 'Z' when dout='1' else '0';

There are also sometimes optional internal pull-ups, but they are not meant to drive external circuits, so an I2C bus will need an actual pull-up resistor.

VHDL std-logic type has 'H' and 'L' values to simulate pull-up and pull-downs. You can write

sda <='H';

in the test-bench to simulate a pull-up.

std_logic is a "resolved" type, a signal can have several drivers, and a resolution function is used to determine the final state : 'Z' + 'H' = 'H' , '0' + 'H' = '0'

Answer 2

1) According to Xilinx, creating a tristate device in VHDL will help you model an open collector/drain output using the following logic diagram:

The VHDL code:

dout <= 'Z' when din='1' else '0';

The Verilog code (even though you specifically asked for VHDL):

always @(ENABLE)
if (ENABLE)
DOUT = 1'bZ;
else
DOUT = 1'b0;

Code, picture, and information can be found here

2) To be able to validate pull-ups, you would instead use logic HIGH and LOW values, i.e. dout <= '1'. You should also review the specifications of your master and slave devices on what pull-up is recommended.

Answer 3

Note that FPGA design tools sometimes provide a specific open-drain primitive in their library. E.g. in Quartus II you can write

LIBRARY altera;
USE altera.altera_primitives_components.all; 
sda: opndrn PORT MAP (
a_in => sda_wire,
a_out => sda_pin
);

This shouldn't make any difference on a bidir IO pin, but it may make a difference if you need to use an output-only pin or migrate your design to ASIC. It makes your code vendor-specific though.