External Memory IC which increments data on a clock pin

Question

I am searching, with no success, in multiple categories of the external memory IC market for a chip that can do the following:

1. Store 1MB of data of 16-bit data
2. This data is stored at specific addresses
3. When I put it into read mode it uses it's 16 output pins to display it's 16-bit values in memory i.e. if the value at address 0x0000 was 0000 0000 0001 0010 this value would be on the pins in +V/0V.
4. When I increment a pin with a clock it will change to address 0x0001 and display that value on it's pins.
5. Preferably has unlimited write cycles like SRAM.
6. Data can be volatile

I can find sram which matches the address on it's input pins and then displays the value at that address to it's output pins. but it won't clock automatically to increment and requires specific reconfiguring of the address pins.

An example that is close is the CY62256NLL-70ZRXIT. but it will not auto increment its address with an external input on its display pins.

Anyone got any suggestions? I suspect it's maybe a type of ram that I am not aware of.

Answer 1

You appear to be describing a FIFO chip, and contrary to the other answers, they do exist as COTS products. For example, IDT has a line of chips of that type. Unfortunately, the 1 MB parts (512k × 18 bits) have prices on the order of $200 in small quantities.

But the rest of your functional description is so vague that I can't be sure. Also, if you have an FPGA in your system anyway, its on-chip block RAM can be configured to do the same thing (assuming that there's enough of it).

Answer 2

What you're describing doesn't exist as a single IC, as far as I know. I have never seen such a device in the last few decades.

That function can readily be implemented with (a) a RAM chip and several 74xxx logic ICs or (b) a RAM chip and a cheap CPLD.

So there would be little incentive for an IC manufacturer to produce a dedicated chip with few and obscure applications that could be implemented with only two ICs.

Answer 3

I'd suggest this 10nS SRAM http://www.issi.com/WW/pdf/61-64WV102416DALL_BLL.pdf with a 20-bit counter in front of it. Perhaps one made of a loadable counter so that you can set up the starting address from you wish to start displaying data, such as 5 of these daisychained: http://www.ti.com/lit/ds/symlink/sn74hc193.pdf or 3 of these much pricier 8-bit parts http://www.ti.com/lit/ds/symlink/sn74as867.pdf

Similar parts are available in other logic families for different speeds.

Might also be less expensive to run two 1M x 8 parts in parallel.