For example let us consider an SR flip flop.
If the clear input is 0 (active low) and preset is 1 this will force the output to go to reset condition (Q=0 and Q'=1.) But if the clear=0 and Preset =1 in this state we give set=1, reset=0 and clock =1 then will both the output be 1 and 1?
If so then using the overriding input when clock =1 is a problem. How to deal with this problem?
There are several ways to deal with this. You could, for example, ignore the \$\overline{Q}\$ output and use only the \$Q\$ output. If you really need the complement then add an inverter.
You could also design the logic around the latch to eliminate the possibility that the asynchronous inputs could be asserted while the enable is also asserted. A better idea might be to prevent the enable from being asserted while either of the asynchronous inputs is asserted. The best approach depends entirely on how you intend to use the latch, and which inputs you want to be prioritized over the others.
By the way, the circuit you present is not an edge-sensitive circuit, it is a level-sensitive circuit. That's why it has an \$enable\$ input rather than an actual \$clock\$ input. I think most of us here would call that a latch rather than a flip-flop.
First of all we have to know about little bit about latches after we going to flipflop.. Basically they are such as: SR, RS JK D T-flipflops
Simple in SR --flipflop first we have to see what components we used in f/f. Basically 4 nand gates with combination of latches with clock pulse is constant with 1. Now we have to check by some methods. Basically. Is drawback of SR-F/F. We basically change clk pulse.. But only we deal to overcome with this situation by using JK-Flipflop..
