Clarification of "strobe pin" 4-bit latch/4 to 16 line decoder

Question

I'm wondering if I can get a specific behavior out of this chip. I have read the data sheet and am having some trouble understanding the usage of the Strobe pin.

CD4515BM96 Datasheet PDF

USE CASE

I'm trying to design a computer from IC chips, using no microprocessors or micro controllers. I would like to use this chip to decode and address upto 16MB of memory split into 512KB SRAM ICs. The data address bus is 24 bits. The highest bit will be used to switch between the high 8MB and low 8MB of memory, the higher 8MB will most likely address removable non-volatile memory. The next highest 4 bits of the data address bus will go to the LY625128SL ic that I would like to ask about. It's outputs will go to the Output Enable/Write Enable pins of the corresponding SRAM. (I might switch them with another IC to get this behavior or i might just have two CD4515BM96)

DESIRED BEHAVIOR

I don't want to worry about pulsing the clock to the strobe pin on this ic, because I belive it may not be necessary. If I simply tie the Strobe pin high will it bypass the latch? I don't need the latch in this chip because I can simply use the output of the data address register storing the four bits it needs.

Is there a better ic for my use case? Is my proposed solution (tying the strobe pin high) correct?

Thank you for your time. I'm but a programmer all this electrical engineering stuff makes my head spin.

Answer 1

If you tie the strobe pin high it will pass the input value through the latch.

This IC is very suitable for your application and your solution is correct.

Answer 2

Strobe simply allows data entry. It can be seen in Fig.13 - Logic diagram. While strobe is 0, data 1-4 are invalid.