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Basically, I have a question regarding the timing of the 74HC574 octal latch. According to the timing diagram, the data pins must be set for so many nanoseconds before the latch pin (rising edge triggered) is pulsed or else the data may not be retained as it should be.

Because the Z80 cannot change the states of its data pins (in which case I could set the data pins with one command, then pulse the latch pin afterwards) this leads me to believe I will have to purchase a parallel IO chip for the Z80 (which I don't want to have to do as that is yet another chip I'll have to add to the motherboard, making it even larger and/or more crammed for space).

BUT, I'm wondering if the I/O address decoding logic will create enough of a delay, as AND gate ICs will create a very small delay (in the nanosecond range as well). The data bus will be directly connected to the 74HC574 and therefore will change the data pins instantly, but the signal which will pulse the data latch pin will have to go through a few AND gates of glue logic which might create enough of a delay that the data pins will be set long enough before the latch pin is pulsed.

I apologize for not being specific in the title, although if you read this you probably agree that my specific question takes a paragraph to explain.

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  • \$\begingroup\$ Why do you think the Z80 can't change the state of its IO pins. \$\endgroup\$ – The Photon Jun 26 '16 at 2:40
  • \$\begingroup\$ By that I meant it cant change the state permanently. With a microcontroller, if you set an output high, it will remain high until you send the instruction to change it low. The z80 will only change the state of its output until the end of the instructions execution. But I actually have found the answer to my own question, I purchased the edge triggered latching 74HC574 while I should have purchased the active high transparent latch 74HC573. I will likely delete this post in a few minutes, sorry for wasting anyones time. \$\endgroup\$ – KeatonB Jun 26 '16 at 2:46
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My, it's been a long time since I worked on Z80 stuff. Perhaps you could use one of the address lines to trigger the latch pin and use one address to set the data then the other to set the latch? You really should check the timing datasheet to see if you even need it though. It looks like you get about 1/2 a clock between the data lines being set and IORQ or WR being set.

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Edit: Oh, I see what you mean about not keeping the data pins constant.

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  • \$\begingroup\$ Thank you! I was unaware of this! I thought I was going to have to order the active high latching 74HC573, but a half a clock cycle should be plenty of time, especially since the Z80 Im using has a max clock of 5MHz. As long as the data pins are set shortly before the IORQ, this should definitely be feasible! \$\endgroup\$ – KeatonB Jun 26 '16 at 2:50
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The 74HC574 is clocked on the low to high edge. If you decode the I/O address to produce an active low output (using eg. a 74HC138) then the write data should be present for ~1.5 CPU clocks before the I/O select goes high at the end of the write cycle. Provided the I/O decode propagation delay is less than 0.5 CPU clocks (100ns at 5MHz) you should be OK.

BTW if you have an NMOS Z80 (eg. Z8400) then all support logic that receives signals from it should be TTL compatible, ie. 74HCT374. If you try to use standard CMOS logic with an NMOS Z80 you may have problems because the Z80 doesn't always pull its outputs up to +5V (they only have to reach 2.4V).

If you have a CMOS Z80 (eg. Z84C00) then you can use either HC or HCT logic.

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