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If you are trying to control memory from a CPU, then if you use two banks instead of one, you can remove the first address line. If you use four banks, then you can also remove the second as well. Why is this?

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    \$\begingroup\$ You need some more details; are you talking about 32-bit processors? Parallel addressed RAM? 8 bits/address? \$\endgroup\$ – Nick T Mar 22 '11 at 1:55
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I think W5VO's reply is a great description of a modern memory system but does not really describe Bank Switching.

You want bank switching when you have a narrow address bus (like 8- or 16-bit) and you want to add more memory. You can then use separate GPIO lines to switch memory chips just like W5VO wrote. You have to be careful because all your pointers are still 8-bit and the switching is manual so you can easily cause a mess.

This technique was/is popular in small micros, but also in 16-bit DOS (it was born on the 80286) and kind of in modern 32-bit processors to address more than 4GB of memory (but here the trick is done invisibly by the kernel and one program can still only see 4GB).

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  • \$\begingroup\$ But how does that reduce the number of address lines? \$\endgroup\$ – 200ok404notfound Mar 23 '11 at 3:16
  • \$\begingroup\$ @2000k404notfound It does allows you to expand beyond the address bus width that is available. I think I do not fully understand your question. If you want to address 4k memory you will need 12 bits of address lines somewhere. The only question is where do you stuff them. \$\endgroup\$ – jpc Mar 23 '11 at 3:21
  • \$\begingroup\$ There are two ways to reduce the number of address lines. One is to divide the memory into rows and columns and latch the row address. Truly random access then requires at least 2 clock cycles but columns inside a row can be accessed quickly. This is how DRAM works. The other method is to have a 32-bit data bus, throw away 2 low-order address bits and only access whole words at once. \$\endgroup\$ – jpc Mar 23 '11 at 3:45
  • \$\begingroup\$ I think it has to do with the last bit of the address. If you have two banks, then you can assign all the even addresses to one line, and all the odd addresses to the other. The last bit tells you if the address is odd or even, but if you use the CS line to select lines, then you don't need it. Does this sound right? \$\endgroup\$ – 200ok404notfound Mar 23 '11 at 3:53
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    \$\begingroup\$ @200ok404notfound: Yes, your description of interleaved memory is valid -- I hesitate to say it is "right" only because bank switching is just as valid. You are describing interleaved memory. W5VO and jpc and supercat are describing bank switching. The Sojourner Mars rover and some TRS-80 Model 100 computers use bank switching between the 16 address pins of the 80C85 and the RAM; they never used interleaved memory. Both techniques have their place. \$\endgroup\$ – davidcary Mar 31 '11 at 20:30
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I'm going to assume that you're talking about parallel memory, and that when you say "use two banks instead of one" you are using two chips that have the same total memory, but each are half as large.

Here's the thing: you can't actually remove that address line from your CPU. It might not go directly to the memory chip, but if you remove it there is no way to distinguish between the two chips. The missing ingredient is the "chip select" function. Most memory chips will have a pin or set of pins that are used to basically tell that particular memory chip that the processor want to talk to only that chip.

Lets consider a simple example: 256 words of memory. This results in an 8-bit address bus.

  • One chip with 256 words: then we are always using only one chip, and it has an 8-bit address.
  • Two chips with 128 words each: Only one memory can be active at the same time, so we will be using the "chip select" pin. The MSB (Most Significant Bit) of the 8-bit address bus will go to the chip select pin on each chip, and the rest of the 7 bits will go to the 7-bit address bus on both chips.
  • Four chips with 64 words each: Only one memory can be active at the same time, so we will be using the "chip select" pin. Some memory chips have multiple chip select pins, but for this example we will assume there is only one. In order to generate the chip select signals for all four chips, we will need a 2-to-4 decoder (also known as a $n\mbox{ }to\mbox{ } 2^{n}$ decoder, row decoder, address decoder - all the same things). This decoder takes the first two MSB from the address bus, and determines which chip select signal should be active. The lower 6 bits of the address go to the 6-bit address bus of all 4 memory chips.

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This is a really simple example, but it scales fine. This is basically the procedure for making multiple memory chips work together to increase the address space.

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  • \$\begingroup\$ Don't you mean that the LSB is used for the chip select? \$\endgroup\$ – 200ok404notfound Mar 23 '11 at 4:02
  • \$\begingroup\$ No, you use the MSB's. That way you're not switching chips every time you increment the address. This makes it much easier to use ROM chips, partially filled address spaces, and devices with a memory bus interface. \$\endgroup\$ – W5VO Mar 23 '11 at 9:09
  • \$\begingroup\$ If you look at page 13 on here the LSB is being used. ece.cmu.edu/~ece548/handouts/13m_arch.pdf \$\endgroup\$ – 200ok404notfound Mar 23 '11 at 9:22
  • \$\begingroup\$ If you want to switch chips every read, then you can use the LSB as CS. You can even use a combination of MSB and LSB or any bits in the address, and it will still work. If you are trying to interleave your chips to get a performance advantage, your system must be able to take advantage of that. \$\endgroup\$ – W5VO Mar 23 '11 at 9:36
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If one has a half-egabyte of byte-addressable memory, there has to be a way of generating a 19-bit address. One nice easy approach is to have a CPU whose address bus has 19 or more address lines (e.g. an 8088). Another approach is to have some of the address lines generated by something other than the CPU's address bus. For example, suppose one has a CPU with a 16-bit address bus and one wants to construct a system with 32K of RAM and ~512KB of ROM. One could use a 13-input AND to detect an access to address 0xFFF0-0xFFFF (one input of the AND would be tied to an 'address valid' signal), and a 4-bit latch to grab the bottom 4 bits of such an address. Fifteen of the ROM address bits would be attached to the CPU's address bus; the other four bits would be connected to latch outputs. The net effect would be that the ROM would be divided into sixteen banks of 32KB each, all of which would be accessed from 0x8000-0xFFEF.

Note that such a system wouldn't quite have 512KB of usable ROM, since accessing any of the last 16 bytes of each 32K bank would switch to one particular 32K bank. Thus, 0xFFF0 would only be available on bank 0, 0xFFF1 from bank 1, etc. Further, in many cases, one would end up having to duplicate some code in different banks. Still, such a system would be quite practical and is in fact very close to what was done in many things like 1980's arcade games.

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  • \$\begingroup\$ That's a pretty quirky bank-switching method. Do you know of any particular systems where this exact method was used? (The bank-switching methods I am familiar with are slightly different from and perhaps even more quirky than this method -- usually the external latch grabbed bits from the data bus rather than the address bus). \$\endgroup\$ – davidcary Mar 31 '11 at 20:13
  • \$\begingroup\$ @davidcary: I don't know the exact details of how arcade games were built, but having 32K of bankable memory was a common pattern. As for using address instead of data, that was a very common technique for Atari 2600 cartridges (which did not have access to a read-write signal) and for Apple II hardware. The Atari 2600 cartridge port includes D0-D7, A0-A12, VDD, VSS, and nothing else. No clocks, read-write controls, or anything. The internal hardware on the 2600 is enabled when A12 is low (regardless of other address bits), so cartridges have 4K of address space. \$\endgroup\$ – supercat Mar 31 '11 at 21:20
  • \$\begingroup\$ @davidcary: Of the cartridges larger than 4K, about 99% of them use addresses 1FF8-1FF9 to switch between two banks (if 8K), or 1FF6-$1FF9 to switch among four (if 16K). Some cartridges have internal RAM, which normally uses different addresses for reading and writing (most such carts 1000-107F for writing and 1080-10FF for reading). I designed a cart for the 2600 which supports reading and writing at the same address; it also allowed hires pixel-plotting to be done in 3 instructions. I built a few prototypes, but someone else came up with a much cheaper way to add RAM to a 2600 cart. \$\endgroup\$ – supercat Mar 31 '11 at 21:24
  • \$\begingroup\$ @davidcary: The approach of using addresses to control functions and ignore the data lines was also popular in Apple II hardware. If one decodes addresses 7Cxx to strobe a latch which grabs 8 bits off the data bus, setting the latches will require two instructions (one to load the data into a register, and one to store it). If one has the latching circuit grab from A0-A7, one can set the latches with one instruction (simply read the address and ignore the result). Alternatively, one can use an 8-bit addressable latch chip and have 16 addresses which set or clear one bit each. \$\endgroup\$ – supercat Mar 31 '11 at 21:29

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