I have 10 numbers saved in RAM. I sorted it using Verilog code and saved output in another RAM. I did simulation and it was doing correct sorting. I synthesized it and generate bit file. Now i want to see whether it performing logically fine after FPGA Implementation or not.But i am confused how will i get output sorted data after FPGA implementation.
Please suggest me how will I get output data after FPGA implementation so that i can check it manually and sure that my CODE is right with FPGA too. Thanks