Verilog and break statements is there a possible alternative?

Question

So I am currently facing an issue where break; statements aren't allowed in verilog? Is there an alternative to this? I've tried disable block_to_disable, but that did not solve anything. Is there possibly an easy fix or is Verilog unable to do this? I only ask since Verilog is a derivation of C. Thank you for your time and help.

module prj2(input [2:0] usr, input button, output reg [6:0] stage);

//input button 

reg currentState = 0; 
reg tracker = 0;
reg stage_0 = 0;
reg stage_1 = 1;
reg stage_2 = 2;
reg stage_3 = 3;
reg stage_4 = 4; 
reg winner = 5; 

/*stage is read in binary 
  stage 0  = 1 
  stage 1 = 2
  stage 2 = 4
  stage 3 = 8
  stage 4 = 16
  stage win[5] = 32  NO STAGE WIN
*/

/*r/p/s is read in binary
0: rock = 1
1: scissors = 2
2: paper = 4
*/

always @ (button) //start of the action section
begin
case(currentState)//draw and loss are the same
/*=======================================================================================*/
  0://using scissors 
    if(usr == 1) 
        begin //beat scissors so use rock 
      tracker <=  stage_1; 
      currentState <= stage_1; //moved to state 1
      stage <= 2; //stage_1
        //disable block_to_disable; 
    end
    else begin//don't move 
        tracker <=  stage_0;
        currentState <= stage_0; //stay in same state
        stage <= 1; //stage_0
        //disable block_to_disable; 
    end
/*=======================================================================================*/
  1://using rock 
    if(usr == 4) begin//beat rock so use paper
        tracker <= stage_2; 
        currentState <= stage_2; //moved to state 2
        stage <= 4; //stage_2
            //disable block_to_disable; 
    end
    else begin //move back to state 1 
         tracker <=  stage_0;
        currentState <= stage_0; //go back to previous state
        stage <= 1; //stage_0 
            //disable block_to_disable; 
    end
    //break;  
/*=======================================================================================*/
     endcase //end case
  end //end begin that comes after always()
endmodule //end the actual module

Answer 1

Verilog is a HDL, not a procedural language. It is not in any way a derivation of C, it just has a vaguely similar syntax, but then so does Java.

Hardware description languages are just that, they are used to describe hardware - what logic circuit, registers, RAMs, etc - if-else statements for example represent multiplexers in digital logic. This is completely different from a procedural language where lines of code are executed on a CPU in turn where you can jump from one bit of code to another (break, goto, if-else).

"Break" statements don't make sense in HDL, because there is nothing to break out from - how would you jump out of a flip-flop? Unless you are meaning 'break' as in asking the FPGA to catch fire or something (which would definitely break it!).

I get the impression you are used to programming in a procedural language and are new to HDL. I would suggest that you go and research/learn the implications of a HDL - there are many tutorials out there e.g. Google "Verilog in one day". You need to understand that the code is not executed, but rather infers logic gates and flip flops (amongst other things). Understanding how HDL is synthesized to an RTL circuit is very important to being able to program with HDL languages.

---

For a case statement, you don't need a break statement, you would simply do:

case (something)
    value: begin
        //do something while "something==value"
    end
    othervalue: begin
        //do something while "something==othervalue"
    end
    default: begin
        //do something while "something" is none of the above
    end
endcase

---

Furthermore, your code doesn't make any sense - nor do some of your comments.

always @ (button) //start of the action section

That basically says implement the following block as combinational logic where the only input is a signal named "button". Yet you have lots of other inputs, so it makes no sense.

Now if you had:

always @ (posedge button)

it would infer a flip-flop whose clock is the "button" signal. The hardware inferred by the case statement would be triggered on the rising edge of the button signal. In reality this would be some combinational logic (which would always be being calculated as its a set of lookup tables), the output of which is latched on to one or more flip flops at the rising edge of the button signal

---

This is yet another example of an X-Y problem - you are telling us what you think the solution is (Y) rather than telling us what you are actually trying to do (X).

Answer 2

Might help to somebody:

When you're using blocking statements that change the 'case' value for your case block, Verilog goes into the next case block according to new 'case' value and executes it.

It looks like this behavior can cause the similar problems, as the absence of break statement in case statements in programming languages, such as C.

However, if you use non-blocking statements, this problem doesn't appear.