I am referring to high speed design with Spartan 6 FPGA. My query is, in design I am having 5V compliant devices (ADC,FIFO memory) and want to interface with 3.3V FPGA spartan 6.

If I opt for simple resistor,diode termination... Is it good option considering sampling rate of ADC 400kHz.

I want to consider all aspects such as power consumption,speed etc in case for Resistor-Diode termination or even for level translator. Please someone help for my understanding.

Attached App Note Link: 5V Tolerance Techniques for CoolRunner-II Devices. https://www.xilinx.com/support/documentation/application_notes/xapp429.pdf

  • \$\begingroup\$ There is no such part as a "Spartan IV". Do you mean the Spartan-6? \$\endgroup\$ – duskwuff Mar 11 '17 at 7:37
  • \$\begingroup\$ Yes, Sorry for mess. (PS. Edited question now) \$\endgroup\$ – Electroholic Mar 11 '17 at 8:09
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    \$\begingroup\$ Are you expecting us to copy the contents of that app note into an answer? Or what exactly is your question? \$\endgroup\$ – CL. Mar 11 '17 at 8:58
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    \$\begingroup\$ It seems to be less complicated to use a level shifter, and this is what Xilinx recommends in the application note you provided. Why not use it? \$\endgroup\$ – Nazar Mar 11 '17 at 15:56

Speed is probably not going to be a big deal, most devices logic level shifting devices now work in the MHz range.

So this is the basic understanding: You cannot exceed any absolute maximum rating for any pin. These ratings are found in the datasheet. On some 3.3 devices they can be 5V tolerant. This is usually not the case on FPGA's because they work with lower voltage levels, I'm not going to look for the datasheet. I spend more than my fair share of time looking at them.

The two methods listed in the app note are for input pins. For output pins either a level shifting circuit with a mosfet or a level shifter IC should do the job.

The most important thing is to make sure you match the ViH and Vil of your ADC (or other device) with that of the shifter (or FPGA). Some digital ADC's might run on 5V but accept 3.3 or 2.4V logic levels for ViH (the threshold voltage for a logic high or '1') so check that first.

Then check the current and make sure you have enough current to drive it, the last thing is to check the maximum clock of the device. If its more that 30-50Mhz then you may need to impedance match the trace with the digital input and output.

  • \$\begingroup\$ Thanks for your answer , what about using resistor - diode termination for adc and other peripherals which includes solenoid valves, memory etc ? board size is main constraint for me due to less size available...hence trying to avoid level shifters.. \$\endgroup\$ – Electroholic Mar 13 '17 at 13:26
  • \$\begingroup\$ That is fine as long as you don't exceed maximum ratings. The size of the resistor needs to be calculated, a dropping resistor is only going to work for an input. For an output there are transistor circuits that are available here and on the web to avoid a level shifting IC, but you will need some kind of active driver. \$\endgroup\$ – Voltage Spike Mar 13 '17 at 15:07

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