I am trying to do some complex, pipelined computations in FPGA that involves storing partial results in block ram and retrieving them later. The problem is, the number of partial results that needs to be stored is very hard to reason about and depends heavily on implementation details. What I want to achieve instead is to divide the circuit into a producer and a consumer, and halt the producer when the system runs out of block ram by stopping its clock, as shown in the ascii drawing below.

input clock  |-------| -----------------------------------------------
-------------| ????? | individually controllable clocks in same domain
             |-------| -----------------------------------------------

Is this achievable? Thanks


In an FPGA design, you don't typically want to actually stop a clock signal.

If you do so, it's called a "gated clock", and having one in your design will make it harder for your synthesis tool to optimize the design and to achieve timing closure.

Instead, you simply de-assert the EN (enable) input on all the flip-flops that you don't want to respond to the clock at some particular time.

In this case, it could mean de-asserting the EN inputs on all the flip-flops in the upstream blocks when the downstream blocks are not ready for new data.

I don't know enough VHDL to write it off the top of my head, but in Verilog, you can infer a flip-flop with an EN signal with something like

always @(posedge clk or posedge reset) begin
    if reset
         out <= 0;
    else if enable begin
         out <= ...
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