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This is the datasheet for 6379A:

datasheet

I looked at the timing charts, but I’m still having trouble figuring out how the IC treats the serial input.

Apparently, SI is sampled at positive clock edge, but what indicates the start of the input? I mean where are MSB and LSB? Also, I don’t get what LRCK does either.

Can someone please explain to me, in simple words, how this IC is used?

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  • \$\begingroup\$ The last 16 bits sent prior to the left/right IO line changing forms the basis of the analogue output. The timing diagram shows MSb and LSb. \$\endgroup\$ – Andy aka Nov 12 '18 at 9:48
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The converter needs one 16 bit word for both channels, L first and then R. LRCK shows to the converter is there coming in data for L or R. Both words come in MSB first, LSB last.

The output of the converter is made from the last fully inputted L+R word pair. The output changes when the input of the next L+R word pair is started. Both channel outputs change at the same time, because people generally do not want any time delay between L and R signals, the timing must be "sample accurate".

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  • \$\begingroup\$ Does this mean the L and R output will have the same value? \$\endgroup\$ – Mah Nov 12 '18 at 11:57
  • \$\begingroup\$ @Mah, no you send one 16 bit data word for channel L and straight away after it another (=arbitary) 16 bit word for R. They will appear in analog outputs when you start to feed the next pair of words, ie. when you turn LRCK again to point L. \$\endgroup\$ – user287001 Nov 12 '18 at 12:01
  • \$\begingroup\$ What if I don't care about the other output? Do I have to wait 16 clocks to write to the output that I want? \$\endgroup\$ – Mah Nov 12 '18 at 12:12
  • \$\begingroup\$ @Mah Unfortunately the datasheet does not specify a way to bypass one channel transmission. If you have one IC to do an experiment you can test, if shortening the R channel transmission period to 1 clock works. No quarantee of the usability of the result. \$\endgroup\$ – user287001 Nov 12 '18 at 12:25

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