# CMOS Inverter Circuit Analysis

So I have a circuit shown below, that looks to me likes it's a CMOS inverter circuit. In this question, we're asked to find the current and voltage across drain-source voltage of the NMOS component.

The values given for the PMOS are as follows:
VDD = 5.003V
VT,pmos = -509mV
µpCox = 101µV/A2
W/L = 2µm/1µm
Lambda = 0V-1

Likewise for the NMOS:
VT,nmos505mV
µpCox = 209µV/A2
W/L = 9µm/1µm
Lambda = 0V-1

Here's the schematic:

So in my attempt to figure this out on my own, I got this:
Clearly, VS of the PMOS = 5.003V
Now after this is where I start to really question myself, and end up going in circles.If I assume that VG = VD based on the circuit diagram, then VGS and VDS are going to give the same value. Won't that then mean the PMOS is cut off?

I've also simulated the circuit in LTSpice. This gives VGSDS as the same value. Which appears to approximately be the source voltage minus the threshold voltage, but a little different. Here's that diagram and the related info it obtains.

Any help is appreciated. Especially in any conceptional mistakes or general assumption methods for the future!

• Your PMOS in the simulation is connected backward. – G36 Apr 6 '19 at 22:19
• Wait really? What way should I have it hooked up? – That_one_guy Apr 7 '19 at 17:33
• Notice the arrow symbol on a PMOS and compare it with your schematic and LTSpice. – G36 Apr 7 '19 at 17:44
• That's annoying alright! But I don't think I can change that. Any time I try to change it's orientation, it just changes the entire PMOS not the arrow symbol :( – That_one_guy Apr 7 '19 at 19:20
• The "arrow"-connection on the pmos is the bulk, and that should be connected to the most positive voltage to avoid forward biasing the body diode (most negative for nmos). In your circuit, the bulk is connected to the output, but it needs to be connected to 5.003V instead. Your pmos needs to be flipped vertically (That's what G36 meant). – Sven B Apr 8 '19 at 8:14

There is about 4 volts across the 2 FETs.

Give the current is the same, we can write

Kp * 2 * VeffectiveP^2 = Kn * 9 * VeffectiveN^2

And VeffectiveP + VeffectveN = 4

• Do you understand this information? – analogsystemsrf Apr 8 '19 at 4:46

Like any other analog circuit, you should try to deal with these problems as if it is a big puzzle of voltages and currents. You kind of need to solve them simultaneously, and the "shapes of the puzzle pieces" are the voltage-current equations of each circuit component.

In this case, when looking at the currents flowing through the circuit, you can notice that the gates do not draw any current, so the current only flows from M2 source -> M2 drain -> M1 drain -> M1 source and back up through V1 (currents always flow in loops). The important part is that it is the same through M1 and M2.

We know that both transistors are in saturation ($$\v_{DSn} = v_{GSn}\$$ and $$\v_{DSp} = v_{GSp}\$$), so you can use the following (simple model) equations:

$$i_{Dn,Dp} = \mu_{n,p}C_{ox}\cdot \frac{W}{2L}(v_{GS}-v_{TH})^2(1+\lambda_{n,p} v_{DS})$$

We know that $$\i_{Dn} = i_{Dp}\$$, and we also know that $$\v_{GSn} - v_{GSp} = 5.003V\$$. This should be enough information to calculate both current and voltage.