Synthesis output for the following verilog code

Question

I have a somewhat stupid question as I am still a noob. So bear with me.

If I have the following statement in Verilog:

input rdy,in;
reg o;
always @(posedge clk)
begin
   if (rdy) o<=in;
end

I am wondering what the synthesis output look like. Would a mux be instantiated in front of the D flip-flop by the synthesis tool?

In other words, is there a need for me to create a combinational block that take i, o and rdy as input and generate a temp signal that feeds the input of d flip flop?

Answer 1

There are two possibilities for Synthesiser to explore which may depend on the tool/optimizations used:

1. The reg o becomes a flip-flop with a 2:1 mux 'in front of it'. The two inputs of the mux will be: The input in and the output of reg o flip-flop fed back. And the mux will have rdy as select signal.

2. The reg o becomes a flip-flop with rdy as clock enable. And in as the D input.