Warning about unused input pin with Verilog 2D array declaration

Question

I want to declare a 2D array in Verilog, and based on the array's row and column, I will be able to access the values. A warning comes in the console showing one of the input pins not being used.

module maze_init(row,col,dataout,clk,start);
    
    input clk;
    input start;
    input [2:0]row;
    input [2:0]col;
    output reg dataout;
    
    //grid initialization placing 1 and 0 to 
    wire grid[4:0][3:0];
    
    assign grid[0][0]=1;
    assign grid[0][1]=0;
    assign grid[0][2]=1;
    assign grid[0][3]=1;
    assign grid[1][0]=0;
    assign grid[1][1]=1;
    assign grid[1][2]=1;
    assign grid[1][3]=0;
    assign grid[2][0]=1;
    assign grid[2][1]=1;
    assign grid[2][2]=0;
    assign grid[2][3]=1;
    assign grid[3][0]=0;
    assign grid[3][1]=1;
    assign grid[3][2]=1;
    assign grid[3][3]=1;
    assign grid[4][0]=1;
    assign grid[4][1]=0;
    assign grid[4][2]=1;
    assign grid[4][3]=1;
    
    always@(posedge clk)begin
        if(start) dataout<=grid[row][col];
        else dataout<=0;
    end
endmodule

Is my array definition being wrong or what?

This is the warning that I receive:

Answer 1

col is declared as as 3-bit input port. This means it can have 8 possible values: 0-7. You are using this as the index into the 2nd dimension of the 2D grid wire. That dimension has 4 possible index values: 0-3.

Therefore, to access indexes 0-3, you only need col to range from 0-3. This means that col values 4-7 are unused, which means that col[2] bit is unused and it is not driving any logic. That explains the warning message for col[2].

Changing the input bit width should eliminate this warning: input [1:0]col;

The warning message regarding row[2] is not as obvious. To access all indexes of the 1st grid dimension, you really do need row to be 3 bits. The last row is 4, which requires 3 bits (3'b100). Not all the values of row are used (5-7), but row[2] is driving some logic.

Keep in mind that these are just warnings. The simulation and synthesis may behave as you intended.