I'm designing an interface in VHDL that connects to a bidirectional signal. However my experience in the dynamics of Hardware Design is limited. What I have at the moment is below:
Within the Red box is what's on the FPGA, outside of that are electrical components.
The RX module looks for a LOW signal for a start bit. To avoid interference between the TX module and the RX module: I placed a Mux controlled by the TX module to pass HIGH whenever it is transmitting.
The external circuitry ensures my TX never drives the line HIGH so to avoid shorts.
When the RX and TX modules are separate, they function perfectly. The RX receives and reads the signal properly and the TX transmits (not into the bidirectional line; instead: my oscilloscope) perfectly. However, closing the switch to combine the two is a catastrophe. The RX Module just seems to become non responsive.
I'm not sure if this is an overall design problem, or something small and stupid with my VHDL.
So is this an acceptable method in interfacing to a bidirectional signal? I have the feeling there is something very wrong in my setup. I'm just looking for suggestions, criticisms, or overall ideas.
If this is indeed an alright setup, then at least I can have confidence in investigating the VHDL for the issue myself, and knowing that my efforts will not be in vain due to an inherently faulty overall design.
Googling: "Interfacing to a bidirectional bus" seems to suggest Tri-State buffers. Is this a better approach?
I feel obnoxious bugging you guys constantly due to lack in a conceptually understanding, so if I could get a suggestion on books or various research sources for conceptually designing hardware, then that would be fantastic.