I have a question on metastability and clock crossing domain.
I need to deserialize a bitstream out of an ADC.
TXCLK, TXOUT1, INCLK are the outputs of the ADC.
So the idea was to register the DATA TXOUT1 on a shift register clocked by TXCLK then capture the parralelized data on every rising edge of INCLK and then write the captured data on an asynchronous FIFO (two independent clocks).
My problem is that the module SHIFT REGISTER is clocked on TXCLK and the module CAPTURE is clocked on INCLK.
INCLK is way slower than TXCLK and i don't know if i will face metastability problems crossing from a fast clock domain (TXCLK) to a slow clock domain (INCLK)
\$\begingroup\$
\$\endgroup\$
Add a comment
|
1 Answer
\$\begingroup\$
\$\endgroup\$
4
You say that TXCLK and INCLK both come from the ADC, so they shouldn't be asynchronous with respect to each other. They should be derived from a common internal source, which means they really belong to the same clock domain, and there's no reason to expect any issues with metastability. See whether the ADC datasheet (which you haven't provided) confirms this.
You do need to be careful not to introduce excessive skew between the two clocks, either in the PCB wiring between the two devices, or inside the FPGA.
answered Mar 15, 2018 at 11:27
-
2\$\begingroup\$ If this is the case, OP will need to add a timing constraint that relates the two clocks to the P&R knows to maintain their relationship. \$\endgroup\$ Commented Mar 15, 2018 at 12:40
-
\$\begingroup\$ So with the data datsheet T1 > 2,09 ns and T2 is around 7 ns for fINCLK= 40 MHz and for fTXCLK = 320 MHz (but tipically i will work at fINCLK= 25 MHz and fTXCLK = 200 MHz) if i am sure that the data that i am sampling at the rising edge of INCLK is stable i don't need to care about the crossing clock domain? If T1 and T2 respect the hold and setup time of the flip flops inside the FPGA ? Do we find the setup and hold time of the flip flops in the datasheets? \$\endgroup\$– the dudeCommented Mar 15, 2018 at 13:06
-
\$\begingroup\$ If you want to discuss the details, please provide a link to the full datasheet for the ADC. With regard to your last question, no, you need to specify the relationship between the signals in the timing constraints, and let the synthesis tools deal with the low-level details such as setup and hold times inside the FPGA. \$\endgroup\$ Commented Mar 15, 2018 at 13:14
-
\$\begingroup\$ Never mind, I found it in your original question in this chain. \$\endgroup\$ Commented Mar 15, 2018 at 14:54