Why are LEDs on after executing this? LEDs on pattern is 1010:
module test(input clk,
input reset,
output reg[3:0] ledss
);
wire[4:0] dataread;
assign dataread=4'bzzzz;
always @(posedge clk)
begin
if(dataread)
begin
ledss<=4'b1010;
end
end
endmodule
When you set a signal in Verilog to z, you're allowing some external device to drive it high or low. In the physical implementation, if there isn't any actual device driving the net, then you're allowing random static electricity to drive it to either 0 or 1. You shouldn't expect to see an actual "Z" state in the physical circuit.
On top of which, in comments, you said this was implemented on an Altera FPGA. Recent FPGAs (since 1995 or so) generally don't implement actual tri-state logic on internal nets. If you design a multiply connected bus with tristate in your Verilog, the physical implementation will use multiplexers to approximate the effect of the tristate logic. But there will never be an actual moment when the net is un-driven in the actual FPGA.
Since you didn't specify whether you wanted a 0 or a 1 driven on those nets when your main driver applied "z", the synthesis tool was free to drive them to either 0 or 1 and had no way of knowing which you wanted.
dataread will never be z. You should read about the memory behavior in the Altera documentation. But there isn't even a read_enable input to the memory, so it will likely just output the value from whatever address it is given, even if you're also doing a write at the same time. You need to keep track in your own logic when the address given is something you want to read, and only act on the output of the memory when it makes sense to do so.
\$\endgroup\$
Commented
Jul 17, 2019 at 21:14
datareadis 5-bit wide, but you assign only 4 bits of it. \$\endgroup\$datareadlines? \$\endgroup\$