Sequential logic in VHDL

Question

Does anyone know of a way I can use sequential statements in VHDL without using the traditional if, case, when statements?

I am building an 8 bit word splitter that will then pass a 4 bit nibble to a hamming encoder, then after that, will send the other 4 bit nibble to the hamming encoder.

I cannot for the life of me figure out how to use the same parity bits on both 4bit nibbles to give separate outputs and in the same process.

the only thought I have is that instead of writing for example P1 <= nibble3 xor nibble5 xor nibble7 -- would be to use the truth table and then use a when statement?

thanks

Answer 1

One of the best pieces of advice my FPGA mentor gave me was

"let the tool do the thinking for you"

At the end of the day, the tool is going to be converting the code you write into boolean algebra in any case. You don't need to do its job for it. There are many many ways to produce the same result in HDL. Choose the way that makes sense to you, and is clear to whomever is going to read the code later (you or someone else).

If you code it the way you think about it, there will be fewer errors than if you try and code in an impressive-but-unintuitive way. There is no need to be fancy in the code. Just code it how it is, even if it's longer, you really don't need to optimise for disk space! It will all end up in the same way at the end of the day. And it will be less error prone, and easier to maintain if you leave the tool to do its job.

Answer 2

Write a process, write a case, just latch the information you need in your process:

p_main: process(clk, reset_n)
  type t_nible_state is (firstnible, secondnible);
  variable r_nible_state : t_nible_state;

  variable r_latchednible : std_logic_vector(7 downto 0);
  variable r_latchedparity : std_logic;

  variable nibletosend : std_logic_vector(3 downto 0);
  variable paritytosend : std_logic;
  variable niblevalid : boolean;

begin

  if reset_n = '0' then
    r_nible_state := firstnible;
    r_latchednible := (others => '0');
    r_latchedparity := '0';

    nibleoutput <= (others => '0');
    parityoutput <= '0';
    niblevalidoutput <= false;

  elsif rising_edge(clk) then
    nibletosend := (others => '0');
    paritytosend := '0';
    niblevalid := false;

    case r_nible_state is
      when firstnible =>
        if bytevalide then -- might not be needed if data is valid every two clock cycles
          r_nible_state := secondnible;

          -- just latch all information you need about both nibles dependent on
          -- the input byte, this includes any parity bits for both this step
          -- and the next
          -- if regs are a problem, but gates are not, latch the
          -- inputbyte, determine parity two times using logic
          r_latchednible := inputbyte(7 downto 4);
          r_latchedparity := secondnibleparity(inputbyte);

          nibletosend := inputbyte(3 downto 0);
          paritytosend := firstnibleparity(inputbyte);
          niblevalid := true;
        end if;
      when secondnible =>
        r_nible_state := firstnible;

        nibletosend := r_latchednible;
        paritytosend := r_latchedparity;
        niblevalid := true;
    end case;

    -- you can put the hamming encoder here using nibletosend
    -- or move to the next block
    nibleoutput <= nibletosend;
    parityoutput <= paritytosend;
    niblevalidoutput <= niblevalid;

  end if;

end process;

Code is untested, but the idea should be simple enough.