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The question in my textbook was:

Design and implement a Serial 2’s Complementer with a Shift Register and a flip–flop. The binary number is shifted out from one side and it’s 2’s complement shifted into the other side of the shift register.

I got the solution but I was curious to know the Verilog implementation of it. How do I do that? circuit diagram

This is the solution.

EDIT: my actual circuit diagram. My circuit diagram

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  • \$\begingroup\$ Why is your output fed back to the input? \$\endgroup\$
    – Shashank V M
    Commented Nov 11, 2020 at 14:44
  • \$\begingroup\$ Where did you get your solution from? \$\endgroup\$
    – Shashank V M
    Commented Nov 11, 2020 at 14:48
  • \$\begingroup\$ @ShashankVM because they have asked to \$\endgroup\$
    – Savannah Madison
    Commented Nov 16, 2020 at 11:09
  • \$\begingroup\$ @ShashankVM i did that because i dont have a good quality cam to take the pic of my circuit. \$\endgroup\$
    – Savannah Madison
    Commented Nov 16, 2020 at 13:54
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    \$\begingroup\$ If you feedback, what happens is that: Suppose I load 1010 initially, I will get 0110 serially, which is fed back to the input Then I get 1010 serially at output, which is fed back again. It goes 1010, 0110, 1010, 0110 .... Ah maybe this is the intention. \$\endgroup\$
    – Mitu Raj
    Commented Nov 16, 2020 at 16:57

1 Answer 1

Reset to default
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ESE doesn't promote free coding service, we can only guide. You already have the circuit with you. So look at it and try to code structurally for example -

  1. Design a simple shift register which is loadable with a parallel binary data (tons of references in google).
  2. Design a D flip-flop module with reset (basics).
  3. Instantiate and integrate both of them in a top module.
  4. Just map the signals between your shift register and flip-flop as shown in the figure, imagine them as wires and how you would connect these two hardwares on a breadboard.

Otherwise, understand the functionality and code the complete circuit in behaviour model. You can do design this in Verilog in many ways.

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  • \$\begingroup\$ It would be the binary number whose 2's compliment is serially output if this is implemented using a PISO shift register. \$\endgroup\$
    – Mitu Raj
    Commented Nov 16, 2020 at 14:30
  • \$\begingroup\$ The circuit shows serial output has to be fed back to the input. So tell me what you will do if I want to find the 2's compliment of say no. "1010"? How will you feed it to the shift register in this scenario? \$\endgroup\$
    – Mitu Raj
    Commented Nov 16, 2020 at 14:38
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    \$\begingroup\$ Otherwise, the circuit given by @Savannah has to be wrong. Feed input serially. Take the 2's compliment out serially. No feed back as shown in her circuit. \$\endgroup\$
    – Mitu Raj
    Commented Nov 16, 2020 at 14:42
  • \$\begingroup\$ Yes, I also feel the circuit is wrong. Apparently the OP copied it from here, on page 3. ece.uwaterloo.ca/~msachdev/ECE223/… \$\endgroup\$
    – Shashank V M
    Commented Nov 16, 2020 at 14:43
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    \$\begingroup\$ @MituRaj Thanks for the guidelines.I will try to code and post my code here. \$\endgroup\$
    – Savannah Madison
    Commented Nov 16, 2020 at 15:50

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