FPGA counter works in simlation, not in hardware

Question

I'm trying to implement an synchronous 4-bit counter in Verilog on the DE10-Lite (according to the Intel Lab Exercise 4). The design works fine in simulation (counts from 0-15 repeatedly), but in hardware the loop skips 0 and 8. If I extend the counter to 5 bit, it skips 0, 8, 16, and 24. The pattern is repeatable and the switches are hardware-debounced. I added some input and output timing constraints, but no difference. I'm an FPGA novice, so this is probably something simple. Any help is appreciated. Thanks!

module DE10_LITE_Golden_Top(
  input              [1:0]      KEY,
  output             [9:0]      LEDR,
  input              [9:0]      SW);

  counter_4 c0 (.enable(SW[1]), .resetn(SW[0]), .clk(KEY[1]), .Q(LEDR[3:0]));
  assign LEDR[9:4] = {6{1'b0}};

endmodule

// counter
module counter_4 (
  input        enable,
  input        clk,
  input        resetn,
  output [3:0] Q);

  wire [3:0]   T;

  assign T[0] = enable;
  tFlipFlop   c0 (.T(T[0]),   .clk(clk), .resetn(resetn), .Q(Q[0]));
  assign T[1] = Q[0] & T[0];
  tFlipFlop   c1 (.T(T[1]),   .clk(clk), .resetn(resetn), .Q(Q[1]));
  assign T[2] = Q[1] & T[1];
  tFlipFlop   c2 (.T(T[2]),   .clk(clk), .resetn(resetn), .Q(Q[2]));
  assign T[3] = Q[2] & T[2];
  tFlipFlop   c3 (.T(T[3]),   .clk(clk), .resetn(resetn), .Q(Q[3]));

endmodule

//  t Flip-flop
module tFlipFlop (
  input       T,
  input       clk,
  input       resetn,
  output reg  Q);

  always @(posedge clk) begin
    if(!resetn) 
       Q <= 0;
    else
      if (T) Q <= ~Q; 
  end

endmodule

Edit: Note that I am using the button input as a "clock", there is no other clock involved.

Answer 1

Not trying to diagnose your problem but just looking at the weaknesses of your circuit...

• Don't rely on external hardware debouncing, which for a demo' board is almost certainly just a parallel capacitor. Add a debouncing circuit to your Verilog firmware. There's plenty of explanations and example Verilog on switch debouncing already available through an internet search.

• Your switches change asynchronously to the logic clock, so your circuit can go metastable. You should filter the switch inputs. Don't just put them through two D-type Flip-Flops - that'll bring them into the clock domain but not reject switching noise. A decent debouncing circuit will provide this noise filtering.

• The hardware RC debouncing will produce a slowly-changing signal from the switches when either pressed or released. Ensure that your FPGA's input pins from the switches have Schmitt triggers enabled.

• Your T-type Flip-Flops (TFFs) are toggled on every clock that the switch is pressed for, so the counter will be running fast. I know your question says you don't see this but its still a weakness of the circuit.

If you fix these, you will see new behaviour for your circuit that may or may not have solved your problem. But you will be proceeding from a stable starting point.

Answer 2

It may be something to do with the "clock" signal from your button not arriving to every flop at the same time. There are constraints for clock routing, but I think putting the button input through a synchronizer (usually a 2 or 3 bit serial in-serial out shift register clocked with the system clock) would help, not to synchronize it (since you don't have another clock in your design), but to give the signal a sharp edge. https://www.fpga4fun.com/CrossClockDomain1.html