How can flipflops sense the edges of the signals?

Question

Latches are level triggered and flipflops are edge triggered. Latches have simple gates connected in a fashion such that they can retrieve the state and hence they are level triggered. That's fine. How can flipflops detect the edges of the signal? Is there any combination of gates which could specifically detect the edges (0 to 1 and 1 to 0?)

Answer 1

The SN74HC74 datasheet shows how a flip-flop (here also with set/clear inputs) is implemented:

These boxes are transmission gates, i.e., 1:1 switches like those in the SN74HC4066. Please note that two transmission gates each are combined to work as a 2:1 multiplexer.

When the /PRE and /CLR inputs are inactive (high), all the NAND gates work as inverters.

• When CLK is low, then the two rightmost NAND gates form a loop that keeps the old value:

  

• When CLK is high, then the two leftmost NAND gates form a loop instead:

  

• When CLK switches from low to high, then the leftmost NAND gate (which got its value from the D input) determines the state.

• When CLK switches from high to low, then the upper right NAND gate (which got its value from the left loop) determines the state.

The CLK edge is not really "detected"; the circuit works because the four transmission gates switch at exactly the same time, and because all the NAND gates have a certain propagation delay.

Answer 2

The simplest answer from some point of view is that a flipflop can be thought or being just two latches one after another.

The data passes throuh from input through the first latch when enable is low, and the latched data passes through the second latch when enable is high.

Thus when enable is low, the input only updates trasparently the input of second latch. When enable goes high, the input to second latch stops updating, but the second latch will update output from the first latch. When enable goes low again, the output stops updating from first latch and first latch now passes input transparently again.

So by concatenating two latches that are sensitive to different enable levels (maybe inverted separtely) it creates a flipflop which updates on rising or falling edge depending on which edge you want.

And that's basically just two level sensitive circuits concatenated. For detecting edges, the process is a bit different and used for different purposes - you could simply use an inverter for delaying a signal and have a XOR gate sensing the actual and delayed signals for pulse generation.

Answer 3

Edge-triggered flip-flops are specific instances of a type of logic circuit called "asynchronous state machines". The theory and design of ASMs fills several chapters of a college-level textbook, so we can't get into it here, but it's been touched on several times before:

• What's the standard way to detect a digital signal transition?
• How would I design a clocked D latch from first principals
• *how* are things triggered on clock rise, fall, high or low,

Answer 4

Based on what is written in the text by Thomas Floyd, Fundamentals of Digital Electronics (translated into Italian and published by Principato 1988), my answer is the following: the circuit is called a transition detector. It consists in principle of a two-input AND gate, one input is connected to one or more NOT gates in cascade so as to create a certain delay of the input signal (clock), the other terminal of the AND is connected directly to the input. Due to the delay of the switching, a very short pulse is obtained at the output which enables the following Latch for that short time.