# *how* are things triggered on clock rise, fall, high or low, [closed]

I know the purpose and function of triggering logic , such as a d flip flop, on certain clock conditions. However, what I have not been able to understand is actually how these "triggers" work. i was thinking maybe to do this you just AND the input with the clock, but I don't feel like this is the right way.

Take a look at a diagram of the simplest type of edge-triggered flip-flop, the D Flip-Flop. It's basically an SR Latch with an extra inverter so that S and R are always complementary states, as well as a clock signal input.

What makes it edge-triggered is that when the clock signal is low, the state of the output will not change. It is only when the clock signal is high that the change in state propagates to the output. You can consider the clock input to be an "enable" input, since it functions like an SR-latch (albeit a kind with only one input) when the clock is high.

If there is data waiting on the input while the clock signal is low, the state will only change once clock is brought high, and so we say that the change occurs at the transition from low to high, or the rising edge.

• +1 There is a nice model to play with here falstad.com/circuit/e-edgedff.html – Trevor_G Oct 18 '17 at 21:57
• You are describing a D-type latch, not an edge-triggered master-slave flip-flip. A latch will change its output to follow its input whenever the clock (really "enable") is high, while a true edge-triggered flip-flop changes its output ONLY on the rising edge of the clock, and at no other time. @Trevor's example is a true FF, but it doesn't really answer the OP's question about how it works. – Dave Tweed Oct 19 '17 at 1:53
• @DaveTweed I kind of agree with you, I would agree more if the OPs original question didn't appear to be asking about all types. That's why I only sent him a link instead of answering... I can't really tell what he is asking. ;) – Trevor_G Oct 19 '17 at 1:59

Edge-triggered flip-flops are a special class of asynchronous state machine (combinatorial logic with feedback) that have been specifically engineered so that their output(s) change state only on a particular edge (rising or falling) of one of the inputs, which is designated the "clock" input.

The design of ASMs in general is far too broad to get into here. It's a lot more complicated than the design of synchronous state machines that are based on edge-triggered FFs.