Using Digital Clock Manager with Verilog to generate 25Mhz clock from 32Mhz internal clock

Question

I am writing a VGA driver program in Verilog on a Spartan 3E (FPGA board Papilio one- 500k bundled with LogicStart MegaWIng). The frequency of the internal clock of Spartan 3E is 32MHz. But I need to generate 25Mhz clock to send Vsync and Hsync singnals. I tried to use the Digital Clock Manager (available in Xilinx Papilio boards) by following the tutorial at...

http://www.gadgetfactory.net/2010/08/dcm-digital-clock-manager-tutorial/

However, the tutorial explains by generating a code in VHDL. I followed the same steps with the only change that, I opted for "Verilog" while choosing the language of the code. However the code generated in my case is structurally different from that in tutorial and I am unable to generate a 25 Mhz clock.

I need to know how to use the DCM feature of Xilinx Papilio boards with Verilog to generate 25 Mh clock from internal 32Mhz clock. How to generate the instantiation code and then how to use it in your .v file containing the code that uses the 25Mhz clock?

Addition

I am using ISE Design Suite 14.7. The code that gets generated with the DCM feature used with Verilog is as follows.

// Instantiate the module
DCM32to50 instance_name (
    .CLKIN_IN(CLKIN_IN), 
    .CLKFX_OUT(CLKFX_OUT), 
    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), 
    .CLK0_OUT(CLK0_OUT)
);

I don't know how to use this in my code and that 25Mhz is produced at which pin.

Answer 1

The Instanitation template gives you an example of how to use the core in your project. All you need to do is paste it into your verilog file.

// Instantiate the module
DCM32to50 instance_name (
    .CLKIN_IN(CLKIN_IN), 
    .CLKFX_OUT(CLKFX_OUT), 
    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), 
                         ^ Change the signals in brackets to your signals
     ^ You don't need to change the port names
    .CLK0_OUT(CLK0_OUT)
);

To help you match it up with the tutorial, in VHDL, it looks like this:

DCM32to50_i : DCM32to50 
port map (
CLKIN_IN        => CLKIN_IN,
CLKFX_OUT       => CLKFX_OUT,
CLKIN_IBUFG_OUT => CLKIN_IBUFG_OUT,
CLK0_OUT        => CLK0_OUT);
                         ^ Signal name you can make what you want.
  ^ Port name doesn't change

CLKIN_IN is your input 32 Mhz clock
CLKFX_OUT is the new 25 Mhz clock
CLKIN_IBUFG_OUT is a buffered version of your 32 Mhz clock
CLK0_OUT is your input clock at 0 phase (basically your input clock again).

Answer 2

'Instantiation template' is just an fancy way of saying that it is giving you a code example.

Verilog names signals work like .input_or_output_name( my_signalname) Like .clock(my_clock_signal) So their instantiation template looks like this:

//  DCM32to50 is the type of thing you want one of, 'instance_name' is what it will be called 
//  in the original instantiation template, I've changed it to 'my_dcm' 
//  
DCM32to50 my_dcm ( .CLKIN_IN(CLKIN_IN), // Clock input (32MHz)
               .CLKFX_OUT(CLKFX_OUT),  // Clock fx output 
               .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT), // loop through of the clock you put in 
               .CLK0_OUT(CLK0_OUT) ); // Clock 0 

You can check in core generator what clock fx, and clock 0 are. I expect clock 0 is your 25Mhz clock.

So if your top level looks like this now

module toplevel(
   input wire clk_in,
   output reg [7:0] output
   );

always @(posedge clk_in)
begin
// do some stuff
end 
endmodule

You can put the dcm in like this

module toplevel(
   input wire clk_in,
   output reg [7:0] output
   );

wire slow_clk, clk_fx, clk_loopthrough;

DCM32to50 my_dcm ( .CLKIN_IN(clk_in), // Clock input (32MHz)
                  .CLKFX_OUT(clk_fx),  // Clock fx output 
                  .CLKIN_IBUFG_OUT(clk_loopthrough), // loop through of the clock you put in 
                  .CLK0_OUT(slow_clk) ); // Clock 0    

always @(posedge slow_clk) //! NOTE THIS IS NOW USING THE CLOCK FROM THE DCM
begin
// do some stuff
end 
endmodule