I'm just starting out in the world of FPGAs. I've picked up a Mojo running a Spartan-6 from Xilinx and I'm attempting to create an arbitrary clock for use with a SENT peripheral. At this point I haven't made it beyond attempting to generate a tick clock (eventually 1.2us) from the base clock (50MHz). I'm using the divider below to take the 50MHz clock as an input and currently divide by 500 which should provide a 100kHz output that I'm feeding directly to a pin connected to my logic analyzer.
File: divider.v
module divider (
input clk, // clock
input rst, // reset
output reg out
);
parameter DIVIDER = 500;
reg [15:0] count = 0;
always @(posedge clk) begin
if (rst == 1) begin
out <= 0;
count <= 0;
end
else begin
if (count == (DIVIDER - 1)) begin
out <= 1;
count <= 0;
end else begin
out <= 0;
count <= count + 1'b1;
end
end
end
endmodule
File: mojo_top.luc
module mojo_top (
input clk, // 50MHz clock
input rst_n, // reset button (active low)
output led [8], // 8 user controllable LEDs
input cclk, // configuration clock, AVR ready when high
output spi_miso, // AVR SPI MISO
input spi_ss, // AVR SPI Slave Select
input spi_mosi, // AVR SPI MOSI
input spi_sck, // AVR SPI Clock
output spi_channel [4], // AVR general purpose pins (used by default to select ADC channel)
input avr_tx, // AVR TX (FPGA RX)
output avr_rx, // AVR RX (FPGA TX)
input avr_rx_busy, // AVR RX buffer full
inout sent0
) {
sig rst; // reset signal
sig data[12];
.clk(clk) {
// The reset conditioner is used to synchronize the reset signal to the FPGA
// clock. This ensures the entire FPGA comes out of reset at the same time.
reset_conditioner reset_cond;
}
divider tick_clock(.clk(clk), .rst(rst));
always {
sent0.enable = 1;
sent0.write = tick_clock.out;
reset_cond.in = ~rst_n; // input raw inverted reset signal
rst = reset_cond.out; // conditioned reset
led = 8h00; // turn LEDs off
spi_miso = bz; // not using SPI
spi_channel = bzzzz; // not using flags
avr_rx = bz; // not using serial port
}
}
What I'm seeing though is that while the clock signal outputs a 100khz waveform as expected it drops out periodically. I haven't been able to draw any conclusions as to why this is happening.
I am expecting a semi-clean 100khz waveform with the supplied code.
I've been banging my head hard against this for a while but I can only assume that it's my lack of Verilog experience that's getting me and not anything to do with the hardware that I am attempting to use. This seems to be similar to existing examples for UART and I2C master modules. But there must be a small detail that is missing.
Can anyone offer any advice regarding producing a clean clock signal to drive an output pin?
