# syntax error verilog code

this sub-code that read the selection line s4-s1 and take the summation of a,b in the selection line =0000, When running this code in ISE project negotiator it gives syntax error tell " Syntax error near "=" " in the line z=0 in the if statement

can you tell me why ?

module one1(a,b,s1,s2,s3,s4,f );
input s1,s2,s3,s4;
input [3:0] a,b;
output reg [3:0] f;

reg  z,n,c;

//0000

if ({s4,s3,s2,s1} == 4'b0000)
begin
assign {c,f}= a+b;
if (f==0)
z=1;         //here is the error
else z=0;
n=f[3];
end

endmodule


Two problems:

1. You need to wrap an always block around your combinational logic. Something like always @* begin

then put your if statement in there.

1. You can't assign a wire inside an always block. you need a reg.
• "you need a reg."... or move the assign statement outside the if block. – The Photon Apr 11 '15 at 18:44