How to use simple generated clock in Verilog Code Vivado 2015.2

Question

I am new to FPGAs. I am using an Artix-7 that comes in the Nexys4DDR, and I am programming in Verilog. I want to create a simple D Flip-Flop that will be triggered by a CLK of 50MHz. The CLK in the board comes in through pin E3 and it is 100MHz, I understand I can divide by 2 this clock in the Verilog code itself, but I thought I wanted to use a derived clock from the 100MHz. So I do this in the Constraint file:

Clock signal

set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; 
create_clock -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
create_generated_clock -name clkdiv2 -source [get_ports CLK100MHZ] -divide_by 2 [get_pins REGA/Q]; 

How can I use the generated clock in my Verilog code? This is probably a very simple question, but how can I take the Q pin of the REGA and use it as my clock in the D Flip-Flop?, how can I complete this design? Do I have to instantiate REGA? If so, how? I have tried many ways, but none work. Thank you for your help.

module D_ff_behavior
    (
        input D, 
        input CLK100MHZ,
        output reg Q
     );

wire clk_div_2;

always @ (posedge clk_div_2)
    Q <= D;

endmodule

Answer 1

Constraints file is only used to apply various constraints on the design.

But the code which generates 50 MHz clock needs to be written by you.You can use a frequency divide by 2 code

wire clk_50MHz;

always @(posedge clk_100MHz)
clk_50MHz <= ~clk_50MHz;

But to let xilinx know that this clk_50MHz is not a normal signal,you need to let xilinx know that this clk_50MHz is a generaed clock constraint in xdc/ucf

Answer 2

You could always just use the enable line on a DFF instead of mucking about with the clock frequencies and perhaps forcing the a signal not routed to be a clock to be used as a clock.

Count the 100MHz pulses, and every time it hits 2 (or any divider), turn another signal on. This other signal then enables your DFF. This way you have your stable 100MHz clock that is properly routed in the FPGA fabric, and it is more flexible as you can create other dividers as well. You could do it something like this:

reg counter;
wire enable_50MHz;

always @(posedge clk_100MHz)
   counter <= counter + 1;
end

assign enable_50MHz = (counter == 1'b1);